BTW, add a missing module (L2lCheckCKeyWord) introduced in the previous change
(necessary for the v6 rdbg plugin)

which was not even compiling...

also:
 -2cw7: fix the generated script
 arduino dir: minor fixes

with recursive clock depende ncies.

nb : i have changed the var name in the generated nodes, which was a bad idea
(=painful to get it rigth again).

I have duplicated the interpretation function SocExec.soc_step
into a CPS SocExecDbg.soc_step

One day I migth only keep the dbg one.

Reference Manual enhancements.

so that w7/lesar can help otawa/ilp to prune path in the binary.

nb : not working on the convertible example:
 - sometimes the module name still appear in the ident (enums)
 - clocks are not well supported by Lesar actually. More thinking is necessary.

Because otherwise, V4 ec tools behaves strangely.

generates unvalid C code.

The bug was appearing a node was called on a non base clock that was
existing in the called nodes (name clash). Typically, it occurs on
recursive node called on some non-trivial clocks.

Also, use maps instead of list to hold the substitution between
params and args.

More precisely, I missed clock in the ve_clk field of val_exp.

and replace enumerated clock in the var_info even if it does not
appear in a val_exp.

nb : luciole-rif is now  in the rdbg repo.

var_info appears in
- node decl
- left var
- static args

not yet working. I commit as Ive fix a missing dep on WenOnId in the _oasis.

More precisely, transforms equations of the form

   y = x when Toto(c);

into

   x when Toto_c ;
   Toto_c=Toto(c);

Rationale: the << normal mode >> (i.e., not translating enums) was
not even accessible!

('::' vs '__')

soc2c -2cw7: use mkff+fixffx+arm.looploc to fix extern lib calls.

The bug was (in soc2c.ml::137) that, for array of instances of size
n, it was generating n+1 initialisations, causing a seg fault.

Factorize duplicated code in gen_loop_file and gen_loop_file4ogensim
along the way.