Because otherwise, V4 ec tools behaves strangely.

generates unvalid C code.

The bug was appearing a node was called on a non base clock that was
existing in the called nodes (name clash). Typically, it occurs on
recursive node called on some non-trivial clocks.

Also, use maps instead of list to hold the substitution between
params and args.

More precisely, I missed clock in the ve_clk field of val_exp.

and replace enumerated clock in the var_info even if it does not
appear in a val_exp.

nb : luciole-rif is now  in the rdbg repo.

var_info appears in
- node decl
- left var
- static args

not yet working. I commit as Ive fix a missing dep on WenOnId in the _oasis.

More precisely, transforms equations of the form

   y = x when Toto(c);

into

   x when Toto_c ;
   Toto_c=Toto(c);

Rationale: the << normal mode >> (i.e., not translating enums) was
not even accessible!

('::' vs '__')

soc2c -2cw7: use mkff+fixffx+arm.looploc to fix extern lib calls.

The bug was (in soc2c.ml::137) that, for array of instances of size
n, it was generating n+1 initialisations, causing a seg fault.

Factorize duplicated code in gen_loop_file and gen_loop_file4ogensim
along the way.

by
- remove duplication (add a profile_info function ine Lv6Verbose
- be more efficient (computing Sys.time only when necessary
- control the time-profiling printing via the -dbg flag "profile", and
  not the verbosity level

I was re-implementing an inneficient topological sort there (using a
linear list instead of logarithmic map). I win 1s on tri.ec (~8000
locals).

I did a map instead of a fold when checking for the absence of cycle.
On programs with 10 000 of equations, I go from 150s to 5s.

Also, force a workflow (via a lock file named commited) that make
sure that the content of lv6version.ml is always correct xrt shat and
git commit number.

as an opam package in the verimag opam repo.

Ditto for Misc and Compile