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verimag
synchrone
sasa
Commits
ffd3f7d7
Commit
ffd3f7d7
authored
Apr 19, 2022
by
erwan
Browse files
fix: -is/-gis avoid a division by 0 when used with a #simu < 100
parent
2440d90f
Pipeline
#96688
passed with stages
in 4 minutes and 25 seconds
Changes
1
Pipelines
1
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Inline
Side-by-side
lib/sasacore/worstInit.ml
View file @
ffd3f7d7
(* Time-stamp: <modified the 1
4
/04/2022 (at 1
7
:20) by Erwan Jahier> *)
(* Time-stamp: <modified the 1
9
/04/2022 (at 1
5
:20) by Erwan Jahier> *)
open
Register
...
...
@@ -221,7 +221,8 @@ let (fchc : out_channel -> ('v SimuState.t -> int) -> 'v SimuState.t -> int
map_local_fold
~
f
:
(
fun
p
->
cost
p
,
p
)
~
fold
:
(
fun
(
cpt
,
nl
)
(
c
,
p
)
->
let
n_percent_done
=
cpt
/
(
dmax
/
100
)
in
assert
(
dmax
<>
0
);
let
n_percent_done
=
if
dmax
<
100
then
1
else
cpt
/
(
dmax
/
100
)
in
if
n_percent_done
<>
!
percent_done
then
(
percent_done
:=
n_percent_done
;
Printf
.
printf
"%d%% of the %d simulations have been tryied so far...
\r
%!"
...
...
@@ -321,7 +322,7 @@ let (global : out_channel -> ('v SimuState.t -> int) -> 'v SimuState.t -> int
else
ss_worst
,
worst
in
let
n_percent_done
=
cpt
/
(
dmax
/
100
)
in
let
n_percent_done
=
if
dmax
<
100
then
1
else
cpt
/
(
dmax
/
100
)
in
if
n_percent_done
<>
!
percent_done
then
(
percent_done
:=
n_percent_done
;
Printf
.
printf
"%d%% of the %d simulations have been tryied so far...
\r
%!"
...
...
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