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verimag
synchrone
lustre-v6
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e67cfc5de92f1e2a7fb6321d00d6e3c8a9686547
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12
6-can-not-iterate-over-the-plus-node-as-long-as-it-is-named-plus
add-multi-generation
lustre-mt_omp
master
default
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multi-task
new_branch_name
pascal01
previously_on_no_branch
solve_ident
take-reset-pragma-into-account
tmp
u0
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20
v6.111.3
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untrack *.cm*
clean sligthly
Update the nonreg test reference with the new test case (of issue #6)
Take #reset pragma into account
Add a -lic/--gen-lic option. Now by default, lv6 just check the program syntax.
take-reset-prag…
take-reset-pragma-into-account
Fix the generation of opam packages
Update the nonreg test reference with the new test case (of issue #6)
Merge remote-tracking branch 'origin/6-can-not-iterate-over-the-plus-node-as-long-as-it-is-named-plus'
issue #6 fixed!
6-can-not-itera…
6-can-not-iterate-over-the-plus-node-as-long-as-it-is-named-plus
Prevent the building of the opam packages if not on the master branch
Add a test that fails: lv6 iterate_on_plus.lus -n test -en -exec
Fix the tests that I've broken in 9028b48ed7a2b4c9c62ac8792ca4a15204d05b7c
Add a -lic/--gen-lic option. Now by default, lv6 just check the program syntax.
Example of makefile-based project
Add a (CeCILL) LICENCE file + documenting dirs via README.org files
Rename lus2lic into lv6
Lus2licRun: catch errors properly (duplicating the work done in main.ml).
Add a clock_profile field to soc.t (currently not used, and not filled).
clean-up utils/lustrequiv, and install in the opam bin dir.
The version number was wrongly computed.
An ugly msg was printed in rpesence of -2c when no node was set.
Minor changes of the exemples in the manual
Fix a bug in the C code generator in the --2c-stack mode.
Add a gitlab CI pipeline
merge
Remove useless files
Remove useless files
Merge branch 'master' of gricad-gitlab.univ-grenoble-alpes.fr:verimag/synchrone/lustre-v6
mv README.txt README.md
Delete OCamlMakefile
Delete TODO.org
Minor changes in the arduino demo.
run the tests on crevetete to record the new timings for future comparisons
rdbg-plugin: add events that mimick node calls when array or struct are accessed
Fix the rdbg plugin wrt iterators (was returning no value)
socExecDbg: add events for Assign and clocks
Reflect the changes in rdbg 1.109 done in the Event interface.
Reflect the changes in rdbg 1.109 done in the Event interface.
--expand-node: not all vars were substituted in var_info.clock_eff.
-lv4: expand nodes because array expansion require nodes to be expanded.
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