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verimag
synchrone
lustre-v6
Commits
d6d22abb
Commit
d6d22abb
authored
Mar 18, 2020
by
erwan
Browse files
Doc: fix a typo in an exemple
parent
17162a37
Pipeline
#43264
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in 4 minutes and 39 seconds
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lv6-ref-man/lv6-ref-man.tex
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d6d22abb
...
...
@@ -866,7 +866,7 @@ the behavior of the whole program is unpredictable.
\begin{example}
[Extern Nodes]
\begin{alltt}
\kwd
{
extern
}
\kwd
{
node
}
foo
\_
with
\_
mem(A:int
,
B:bool, C: real)
\kwd
{
returns
}
(X:int
,
Y: real);
\kwd
{
extern
}
\kwd
{
node
}
foo
\_
with
\_
mem(A:int
;
B:bool, C: real)
\kwd
{
returns
}
(X:int
;
Y: real);
\kwd
{
extern
}
\kwd
{
function
}
sin(A:real)
\kwd
{
returns
}
(sinx: real);
\end{alltt}
...
...
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