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verimag
synchrone
lustre-v6
Commits
2d1dd4db
Commit
2d1dd4db
authored
16 years ago
by
Erwan Jahier
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The clock printing was wrong in the code generation.
parent
09b1e4d6
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src/compiledDataDump.ml
+1
-2
1 addition, 2 deletions
src/compiledDataDump.ml
src/getEff.ml
+1
-1
1 addition, 1 deletion
src/getEff.ml
src/test/should_work/fab_test/morel4.lus
+1
-1
1 addition, 1 deletion
src/test/should_work/fab_test/morel4.lus
src/test/test.res.exp
+30
-44
30 additions, 44 deletions
src/test/test.res.exp
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33 additions
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48 deletions
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