m32r.cpu

; Renesas M32R CPU description.  -*- Scheme -*-
;
; Copyright 1998, 1999, 2000, 2001, 2003, 2007, 2009
; Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Mitsubishi
; Electric Corporation.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
; MA 02110-1301, USA.

(include "simplify.inc")

; FIXME: Delete sign extension of accumulator results.
; Sign extension is done when accumulator is read.

; define-arch must appear first

(define-arch
  (name m32r) ; name of cpu family
  (comment "Renesas M32R")
  (default-alignment aligned)
  (insn-lsb0? #f)
  (machs m32r m32rx m32r2)
  (isas m32r)
)

; Attributes.

; An attribute to describe which pipeline an insn runs in.
; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.
; These instructions have O attribute for m32rx and OS attribute for m32r2.

(define-attr
  (for insn)
  (type enum)
  (name PIPE)
  (comment "parallel execution pipeline selection")
  (values NONE O S OS O_OS)
)

; A derived attribute that says which insns can be executed in parallel
; with others.  This is a required attribute for architectures with
; parallel execution.

(define-attr
  (for insn)
  (type enum)
  (name PARALLEL)
  (attrs META) ; do not define in any generated file for now
  (values NO YES)
  (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))
)

; Instruction set parameters.

(define-isa
  (name m32r)

  ; This is 32 because 16 bit insns always appear as pairs.
  ; ??? See if this can go away.  It's only used by the disassembler (right?)
  ; to decide how long an unknown insn is.  One value isn't sufficient (e.g. if
  ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)
  (default-insn-bitsize 32)

  ; Number of bytes of insn we can initially fetch.
  ; The M32R is tricky in that insns are either two 16-bit insns
  ; (executed sequentially or in parallel) or one 32-bit insn.
  ; So on one hand the base insn size is 16 bits, but on another it's 32.
  ; 32 is chosen because:
  ; - if the chip were ever bi-endian it is believed that the byte order would
  ;   be based on 32 bit quantities
  ; - 32 bit insns are always aligned on 32 bit boundaries
  ; - the pc will never stop on a 16 bit (and not 32 bit) boundary
  ;   [well actually it can, but there are no branches to such places]
  (base-insn-bitsize 32)

  ; Used in computing bit numbers.
  (default-insn-word-bitsize 32)

  ; The m32r fetches 2 insns at a time.
  (liw-insns 2)

  ; While the m32r can execute insns in parallel, the base mach can't
  ; (other than nop).  The base mach is greatly handicapped by this, but
  ; we still need to cleanly handle it.
  (parallel-insns 2)

  ; Initial bitnumbers to decode insns by.
  (decode-assist (0 1 2 3 8 9 10 11))

  ; Classification of instructions that fit in the various frames.
  ; wip, not currently used
  (insn-types (long ; name
	       31 ; length
	       (eq-attr (current-insn) LENGTH 31) ; matching insns
	       (0 1 2 7 8 9 10) ; decode-assist
	       )
	      (short
	       15
	       (eq-attr (current-insn) LENGTH 15) ; matching insns
	       (0 1 2 7 8 9 10)
	       )
	      )

  ; Instruction framing.
  ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed
  ; serially (left->right), or two 16 bit insns executed parallelly.
  ; wip, not currently used
  (frame long32 ; name
	 ((long)) ; list of insns in frame, plus constraint
	 "$0"   ; assembler
	 (+ (1 1) (31 $0)) ; value
	 (sequence () (execute $0)) ; action
	 )
  (frame serial2x16
	 ((short)
	  (short))
	 "$0 -> $1"
	 (+ (1 0) (15 $0) (1 0) (15 $1))
	 (sequence ()
		   (execute $0)
		   (execute $1))
	 )
  (frame parallel2x16
	 ((short (eq-attr (current-insn) PIPE "O,BOTH"))
	  (short (eq-attr (current-insn) PIPE "S,BOTH")))
	 "$0 || $1"
	 (+ (1 0) (15 $0) (1 1) (15 $1))
	 (parallel ()
		   (execute $0)
		   (execute $1))
	 )
)

; Cpu family definitions.

; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
; define-cpu.
; ??? Have define-arch provide defaults for architecture that define-cpu can
; then override [reduces duplication in define-cpu].
; ??? Another way to go is to delete cpu-families entirely and have one mach
; able to inherit things from another mach (would also need the ability to
; not only override specific inherited things but also disable some,
; e.g. if an insn wasn't supported).

(define-cpu
  ; cpu names must be distinct from the architecture name and machine names.
  ; The "b" suffix stands for "base" and is the convention.
  ; The "f" suffix stands for "family" and is the convention.
  (name m32rbf)
  (comment "Renesas M32R base family")
  (endian either)
  (word-bitsize 32)
  ; Override isa spec (??? keeps things simpler, though it was more true
  ; in the early days and not so much now).
  (parallel-insns 1)
)

(define-cpu
  (name m32rxf)
  (comment "Renesas M32Rx family")
  (endian either)
  (word-bitsize 32)
  ; Generated files have an "x" suffix.
  (file-transform "x")
)

(define-cpu
  (name m32r2f)
  (comment "Renesas M32R2 family")
  (endian either)
  (word-bitsize 32)
  ; Generated files have an "2" suffix.
  (file-transform "2")
)

(define-mach
  (name m32r)
  (comment "Generic M32R cpu")
  (cpu m32rbf)
)

(define-mach
  (name m32rx)
  (comment "M32RX cpu")