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Sebastien Michelland
binutils-gdb
Commits
8ee9a8b2
Commit
8ee9a8b2
authored
21 years ago
by
Nick Clifton
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Apply m32r patches from Renesas
parent
2f690297
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cpu/ChangeLog
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-0
24 additions, 0 deletions
cpu/ChangeLog
cpu/m32r.cpu
+420
-121
420 additions, 121 deletions
cpu/m32r.cpu
cpu/m32r.opc
+47
-7
47 additions, 7 deletions
cpu/m32r.opc
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491 additions
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128 deletions
cpu/ChangeLog
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8ee9a8b2
2004-02-23 Nick Clifton <nickc@redhat.com>
* Apply these patches from Renesas:
2004-02-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* cpu/m32r.opc (my_print_insn): Fixed incorrect output when
disassembling codes for 0x*2 addresses.
2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* cpu/m32r.cpu : Add new model m32r2.
Add new instructions.
Replace occurrances of 'Mitsubishi' with 'Renesas'.
Changed PIPE attr of push from O to OS.
Care for Little-endian of M32R.
* cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
Care for Little-endian of M32R.
(parse_slo16): signed extension for value.
2004-02-20 Andrew Cagney <cagney@redhat.com>
* m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick
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cpu/m32r.opc
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...
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@@ -27,7 +27,6 @@
*/
/* This file is an addendum to m32r.cpu. Heavy use of C code isn't
appropriate in .cpu files, so it resides here. This especially applies
to assembly/disassembly where parsing/printing can be quite involved.
...
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@@ -49,6 +48,7 @@
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
#if 0
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
#define CGEN_DIS_HASH(buffer, value) \
(X (buffer) | \
...
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@@ -56,7 +56,37 @@
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
#else
#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
#endif
/* -- */
/* -- opc.c */
unsigned int
m32r_cgen_dis_hash (buf, value)
const char * buf ATTRIBUTE_UNUSED;
CGEN_INSN_INT value;
{
unsigned int x;
if (value & 0xffff0000) /* 32bit instructions */
value = (value >> 16) & 0xffff;
x = (value>>8) & 0xf0;
if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
return x;
if (x == 0x70 || x == 0xf0)
return x | ((value>>8) & 0x0f);
if (x == 0x30)
return x | ((value & 0x70) >> 4);
else
return x | ((value & 0xf0) >> 4);
}
/* -- */
/* -- asm.c */
...
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@@ -159,7 +189,11 @@ parse_slo16 (cd, strp, opindex, valuep)
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value &= 0xffff;
{
value &= 0xffff;
if (value & 0x8000)
value |= 0xffff0000;
}
*valuep = value;
return errmsg;
}
...
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@@ -259,10 +293,13 @@ my_print_insn (cd, pc, info)
char *buf = buffer;
int status;
int buflen = (pc & 3) == 0 ? 4 : 2;
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
char *x;
/* Read the base part of the insn. */
status = (*info->read_memory_func) (pc, buf, buflen, info);
status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
buf, buflen, info);
if (status != 0)
{
(*info->memory_error_func) (status, pc, info);
...
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@@ -270,22 +307,25 @@ my_print_insn (cd, pc, info)
}
/* 32 bit insn? */
if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
x = (big_p ? &buf[0] : &buf[3]);
if ((pc & 3) == 0 && (*x & 0x80) != 0)
return print_insn (cd, pc, info, buf, buflen);
/* Print the first insn. */
if ((pc & 3) == 0)
{
buf += (big_p ? 0 : 2);
if (print_insn (cd, pc, info, buf, 2) == 0)
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
buf +=
2
;
buf +=
(big_p ? 2 : -2)
;
}
if (buf[0] & 0x80)
x = (big_p ? &buf[0] : &buf[1]);
if (*x & 0x80)
{
/* Parallel. */
(*info->fprintf_func) (info->stream, " || ");
buf[0]
&= 0x7f;
*x
&= 0x7f;
}
else
(*info->fprintf_func) (info->stream, " -> ");
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