Newer
Older
; bpc = bbpc
(set (reg h-cr 6) (reg h-cr 14))
; psw = bpsw
(set (reg h-psw) (reg h-bpsw))
; bpsw = bbpsw
(set (reg h-bpsw) (reg h-bbpsw))
)
()
)
(dni seth "seth"
((IDOC ALU))
"seth $dr,$hash$hi16"
(+ OP1_13 OP2_12 dr (f-r2 0) hi16)
(set dr (sll WI hi16 (const 16)))
()
)
(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
(begin
(.str sym " $dr,$sr")
(+ OP1_1 op2-r-op dr sr)
(set dr (sem-op dr (and sr (const 31))))
()
)
(dni (.sym sym "3") sym ((IDOC ALU))
(.str sym "3 $dr,$sr,$simm16")
(+ OP1_9 op2-3-op dr sr simm16)
(set dr (sem-op sr (and WI simm16 (const 31))))
()
)
(dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
(.str sym "i $dr,$uimm5")
(+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
(set dr (sem-op dr uimm5))
()
)
)
)
(shift-op sll OP2_4 OP2_12 2 sll)
(shift-op sra OP2_2 OP2_10 1 sra)
(shift-op srl OP2_0 OP2_8 0 srl)
(define-pmacro (store-op suffix op2-op mode)
(begin
(dni (.sym st suffix) (.str "st" suffix)
((PIPE O) (IDOC MEM))
(.str "st" suffix " $src1,@$src2")
(+ OP1_2 op2-op src1 src2)
(set mode (mem mode src2) src1)
((m32r/d (unit u-store (cycles 1)))
(m32rx (unit u-store (cycles 1)))
(m32r2 (unit u-store (cycles 1))))
)
(dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
(NO-DIS (PIPE O) (IDOC MEM))
(.str "st" suffix " $src1,@($src2)")
(emit (.sym st suffix) src1 src2))
(dni (.sym st suffix -d) (.str "st" suffix "-d")
((IDOC MEM))
(.str "st" suffix " $src1,@($slo16,$src2)")
(+ OP1_10 op2-op src1 src2 slo16)
(set mode (mem mode (add src2 slo16)) src1)
((m32r/d (unit u-store (cycles 2)))
(m32rx (unit u-store (cycles 2)))
(m32r2 (unit u-store (cycles 2))))
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)
(dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
(NO-DIS (IDOC MEM))
(.str "st" suffix " $src1,@($src2,$slo16)")
(emit (.sym st suffix -d) src1 src2 slo16))
)
)
(store-op "" OP2_4 WI)
(store-op b OP2_0 QI)
(store-op h OP2_2 HI)
(dni st-plus "st+"
((PIPE O) (IDOC MEM))
"st $src1,@+$src2"
(+ OP1_2 OP2_6 src1 src2)
; This has to be coded carefully to avoid an "earlyclobber" of src2.
(sequence ((WI new-src2))
(set new-src2 (add WI src2 (const WI 4)))
(set (mem WI new-src2) src1)
(set src2 new-src2))
((m32r/d (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32r2 (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
(dni sth-plus "sth+"
((MACH m32rx,m32r2) (PIPE O) SPECIAL)
"sth $src1,@$src2+"
(+ OP1_2 OP2_3 src1 src2)
; This has to be coded carefully to avoid an "earlyclobber" of src2.
(sequence ((WI new-src2))
(set new-src2 src2)
(set (mem HI new-src2) src1)
(set src2 (add new-src2 (const 2))))
((m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32r2 (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
(dni stb-plus "stb+"
((MACH m32rx,m32r2) (PIPE O) SPECIAL)
"stb $src1,@$src2+"
(+ OP1_2 OP2_1 src1 src2)
; This has to be coded carefully to avoid an "earlyclobber" of src2.
(sequence ((WI new-src2))
(set new-src2 src2)
(set (mem QI new-src2) src1)
((m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32r2 (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
(dni st-minus "st-"
((PIPE O) (IDOC MEM))
"st $src1,@-$src2"
(+ OP1_2 OP2_7 src1 src2)
; This is the original way. It doesn't work for parallel execution
; because of the earlyclobber of src2.
;(sequence ()
; (set src2 (sub src2 (const 4)))
; (set (mem WI src2) src1))
(sequence ((WI new-src2))
(set new-src2 (sub src2 (const 4)))
(set (mem WI new-src2) src1)
(set src2 new-src2))
((m32r/d (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32r2 (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
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"push $src1"
(emit st-minus src1 (src2 15)) ; "st %0,@-sp"
)
(dni sub "sub"
((PIPE OS) (IDOC ALU))
"sub $dr,$sr"
(+ OP1_0 OP2_2 dr sr)
(set dr (sub dr sr))
()
)
(dni subv "sub:rv"
((PIPE OS) (IDOC ALU))
"subv $dr,$sr"
(+ OP1_0 OP2_0 dr sr)
(parallel ()
(set dr (sub dr sr))
(set condbit (sub-oflag dr sr (const 0))))
()
)
(dni subx "sub:rx"
((PIPE OS) (IDOC ALU))
"subx $dr,$sr"
(+ OP1_0 OP2_1 dr sr)
(parallel ()
(set dr (subc dr sr condbit))
(set condbit (sub-cflag dr sr condbit)))
()
)
(dni trap "trap"
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC))
"trap $uimm4"
(+ OP1_1 OP2_15 (f-r1 0) uimm4)
(sequence ()
; bbpc = bpc
(set (reg h-cr 14) (reg h-cr 6))
; Set bpc to the return address. Actually it's not quite the
; return address as RTE rounds the address down to a word
; boundary.
(set (reg h-cr 6) (add pc (const 4)))
; bbpsw = bpsw
(set (reg h-bbpsw) (reg h-bpsw))
; bpsw = psw
(set (reg h-bpsw) (reg h-psw))
; sm is unchanged, ie,c are set to zero.
(set (reg h-psw) (and (reg h-psw) (const #x80)))
; m32r_trap handles operating vs user mode
(set WI pc (c-call WI "m32r_trap" pc uimm4))
)
()
)
(dni unlock "unlock"
((PIPE O) (IDOC MISC))
"unlock $src1,@$src2"
(+ OP1_2 OP2_5 src1 src2)
(sequence ()
(if (reg h-lock)
(set (mem WI src2) src1))
(set (reg h-lock) (const BI 0)))
((m32r/d (unit u-load))
(m32rx (unit u-load))
(m32r2 (unit u-load)))
)
; Saturate into byte.
(dni satb "satb"
"satb $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
(set dr
; FIXME: min/max would simplify this nicely of course.
(cond WI
((ge sr (const 127)) (const 127))
((le sr (const -128)) (const -128))
(else sr)))
()
)
; Saturate into half word.
(dni sath "sath"
"sath $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
(set dr
(cond WI
((ge sr (const 32767)) (const 32767))
((le sr (const -32768)) (const -32768))
(else sr)))
()
)
; Saturate word.
(dni sat "sat"
"sat $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 0))
(set dr
(if WI condbit
(if WI (lt sr (const 0))
(const #x7fffffff)
(const #x80000000))
sr))
()
)
; Parallel compare byte zeros.
; Set C bit in condition register if any byte in source register is zero.
(dni pcmpbz "pcmpbz"
((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
"pcmpbz $src2"
(+ OP1_0 (f-r1 3) OP2_7 src2)
(set condbit
(cond BI
((eq (and src2 (const #xff)) (const 0)) (const BI 1))
((eq (and src2 (const #xff00)) (const 0)) (const BI 1))
((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
(else (const BI 0))))
((m32rx (unit u-cmp))
(m32r2 (unit u-cmp)))
)
; Add accumulators
(dni sadd "sadd"
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"sadd"
(+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
(set (reg h-accums 0)
(add (sra (reg h-accums 1) (const 16))
(reg h-accums 0)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
; Multiply and add into accumulator 1
(dni macwu1 "macwu1"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"macwu1 $src1,$src2"
(+ OP1_5 src1 OP2_11 src2)
(set (reg h-accums 1)
(sra DI
(sll DI
(add DI
(reg h-accums 1)
(mul DI
(ext DI src1)
(ext DI (and src2 (const #xffff)))))
(const 8))
(const 8)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
; Multiply and subtract from accumulator 0
(dni msblo "msblo"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"msblo $src1,$src2"
(+ OP1_5 src1 OP2_13 src2)
(set accum
(sra DI
(sll DI
(sub accum
(sra DI
(sll DI
(mul DI
(ext DI (trunc HI src1))
(ext DI (trunc HI src2)))
(const 32))
(const 16)))
(const 8))
(const 8)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
; Multiply into accumulator 1
(dni mulwu1 "mulwu1"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"mulwu1 $src1,$src2"
(+ OP1_5 src1 OP2_10 src2)
(set (reg h-accums 1)
(sra DI
(sll DI
(mul DI
(ext DI src1)
(ext DI (and src2 (const #xffff))))
(const 16))
(const 16)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
; Multiply and add into accumulator 1
(dni maclh1 "maclh1"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"maclh1 $src1,$src2"
(+ OP1_5 src1 OP2_12 src2)
(set (reg h-accums 1)
(sra DI
(sll DI
(add DI
(reg h-accums 1)
(sll DI
(ext DI
(mul SI
(ext SI (trunc HI src1))
(sra SI src2 (const SI 16))))
(const 16)))
(const 8))
(const 8)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
; skip instruction if C
(dni sc "sc"
((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"sc"
(+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
(skip (zext INT condbit))
()
)
; skip instruction if not C
(dni snc "snc"
((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"snc"
(+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
(skip (zext INT (not condbit)))
()
)
; PSW &= ((~ uimm8) | 0xff00)
(dni clrpsw "clrpsw"
((PIPE O) SPECIAL_M32R)
"clrpsw $uimm8"
(+ OP1_7 (f-r1 2) uimm8)
(set USI (reg h-cr 0)
(and USI (reg h-cr 0)
(or USI (zext SI (inv QI uimm8)) (const #xff00))))
()
)
; PSW |= (unsigned char) uimm8
(dni setpsw "setpsw"
((PIPE O) SPECIAL_M32R)
"setpsw $uimm8"
(+ OP1_7 (f-r1 1) uimm8)
(set USI (reg h-cr 0) uimm8)
()
)
; bset
(dni bset "bset"
(SPECIAL_M32R)
"bset $uimm3,@($slo16,$sr)"
(+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
(set QI (mem QI (add sr slo16))
(or QI (mem QI (add sr slo16))
(sll QI (const 1) (sub (const 7) uimm3))))
()
)
; bclr
(dni bclr "bclr"
(SPECIAL_M32R)
"bclr $uimm3,@($slo16,$sr)"
(+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16)
(set QI (mem QI (add sr slo16))
(and QI (mem QI (add sr slo16))
(inv QI (sll QI (const 1) (sub (const 7) uimm3)))))
()
)
; btst
(dni btst "btst"
(SPECIAL_M32R (PIPE O))
"btst $uimm3,$sr"
(+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
(set condbit (and QI (srl QI sr (sub (const 7) uimm3)) (const 1)))