- Jul 08, 2019
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Gwennan Eliezer authored
(I forgot to change it everywhere)
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Gwennan Eliezer authored
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- Jul 05, 2019
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Nathan Rébiscoul authored
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- Jul 04, 2019
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Nathan Rébiscoul authored
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Nathan Rébiscoul authored
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Nathan Rébiscoul authored
Merge branch 'master' of https://gricad-gitlab.univ-grenoble-alpes.fr/verimag/synchrone/sasa into 11-add-lustre-oracles-to-all-examples-of-the-test-directory
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Nathan Rébiscoul authored
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- Jul 03, 2019
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Gwennan Eliezer authored
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erwan authored
Add the doc generation in the test to avoid such CI failueres in the future
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erwan authored
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erwan authored
Add use it to add an oracle to the BFS
- Jul 02, 2019
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erwan authored
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- Jul 01, 2019
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erwan authored
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- Jun 28, 2019
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Gwennan Eliezer authored
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Gwennan Eliezer authored
Took into account Erwan's comments and changed Register module such that the properties are computed on first call (except height that is computed on each call because it depends on the chosen tree's root)
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- Jun 26, 2019
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Gwennan Eliezer authored
- Jun 25, 2019
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- Jun 24, 2019
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- Jun 21, 2019
- Jun 20, 2019
- Jun 19, 2019
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erwan authored
Basically, the idea is to parse the result of the registred ('s -> string) function. For instance if the user define 'v and 'v printer as follows: type state = { a : int ; b : float } let state_to_string s = Printf.sprintf "x=%d y=%f" s.v1 s.v2 pid_x and pid_y will be used as output var names in the RIF outputs. If the user provide no name: let state_to_string s = Printf.sprintf "%d %f" s.v1 s.v2 some names will be invented (pid_v0 and pid_v1)
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erwan authored
All the get_* functions (that are of no interest for users) are now in the Register module.
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erwan authored
Things that are currently broken: - the ability to init vars in the dot - controling the name of local vars in the rif output
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- Jun 17, 2019
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erwan authored
The idea is to use the Obj module (arg !!!), which is safe thanks to the fact that there is now only one register function, which forces all the 'v to be bound to the same type.
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- Jun 14, 2019
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erwan authored
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