New: make the number of nodes accessible from processes (via Algo.card: unit -> int) (f7dc8780) · Commits · verimag / synchrone / sasa · GitLab

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f7dc8780

Commit f7dc8780 authored 5 years ago by erwan

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New: make the number of nodes accessible from processes (via Algo.card: unit -> int)

parent b5770fd6

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Changes 7

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lib/algo/algo.ml 14 additions, 1 deletion

lib/algo/algo.ml
lib/algo/algo.mli 10 additions, 2 deletions

lib/algo/algo.mli
lib/sasacore/sasa.ml 2 additions, 1 deletion

lib/sasacore/sasa.ml
test/bfs-spanning-tree/p.ml 2 additions, 2 deletions

test/bfs-spanning-tree/p.ml
test/dfs/p.ml 2 additions, 2 deletions

test/dfs/p.ml
test/dijkstra-ring/ring.ml 2 additions, 2 deletions

test/dijkstra-ring/ring.ml
test/unison/unison.ml 2 additions, 2 deletions

test/unison/unison.ml

with 34 additions and 12 deletions

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