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verimag
synchrone
sasa
Commits
846ddb10
Commit
846ddb10
authored
6 years ago
by
erwan
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Add a unison exemple
parent
4b296fb5
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test/unison/Makefile
+19
-0
19 additions, 0 deletions
test/unison/Makefile
test/unison/ring.dot
+13
-0
13 additions, 0 deletions
test/unison/ring.dot
test/unison/unison.ml
+36
-0
36 additions, 0 deletions
test/unison/unison.ml
with
68 additions
and
0 deletions
test/unison/Makefile
0 → 100644
+
19
−
0
View file @
846ddb10
DIR
=
~/sasa/_build/install/default
sasa
=
$(
DIR
)
/bin/sasa
# LIB=-I $(DIR)/lib/algo $(DIR)/lib/algo/algo.cmxa
MLI
=
-I
$(
DIR
)
/lib/algo
%.cmxs
:
%.ml
ocamlopt
-shared
$(
MLI
)
$^
-o
$@
test
:
unison.cmxs
$(
sasa
)
ring.dot
clean
:
rm
-f
*
.cmxs sasa
*
.cmi
*
.o
*
.cmx
*
.pdf
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test/unison/ring.dot
0 → 100644
+
13
−
0
View file @
846ddb10
graph
ring7
{
p1
[
algo
=
"unison.cmxs"
]
p2
[
algo
=
"unison.cmxs"
]
p3
[
algo
=
"unison.cmxs"
]
p4
[
algo
=
"unison.cmxs"
]
p5
[
algo
=
"unison.cmxs"
]
p6
[
algo
=
"unison.cmxs"
]
p7
[
algo
=
"unison.cmxs"
]
p1
--
p2
--
p3
--
p4
--
p5
--
p6
--
p7
--
p1
}
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test/unison/unison.ml
0 → 100644
+
36
−
0
View file @
846ddb10
(* Time-stamp: <modified the 07/03/2019 (at 11:31) by Erwan> *)
open
Algo
let
vars
=
[
"clock"
,
It
]
let
m
=
42
let
init_vars
=
function
_
->
I
(
Random
.
int
m
)
let
list_min
l
=
match
l
with
[]
->
assert
false
|
x
::
l
->
List
.
fold_left
min
x
l
let
i
e
v
=
match
e
v
with
I
i
->
i
|
_
->
assert
false
let
new_clock_value
nl
e
=
let
cl
=
List
.
map
(
fun
n
->
i
n
.
lenv
"clock"
)
nl
in
let
min_clock
=
List
.
fold_left
min
(
i
e
"clock"
)
cl
in
min_clock
+
1
mod
m
let
enable_f
nl
e
=
if
I
(
new_clock_value
nl
e
)
<>
e
"clock"
then
[
"incr"
]
else
[]
let
step_f
nl
e
=
function
|
_
->
(
function
"clock"
->
I
(
new_clock_value
nl
e
)
|
_
->
assert
false
)
let
()
=
let
algo_id
=
"unison"
in
Algo
.
reg_vars
algo_id
vars
;
Algo
.
reg_init_vars
algo_id
init_vars
;
Algo
.
reg_enable
algo_id
enable_f
;
Algo
.
reg_step
algo_id
step_f
;
()
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