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verimag
synchrone
sasa
Commits
319660d4
Commit
319660d4
authored
1 year ago
by
erwan
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ci: track a missing file
parent
007efa3a
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Pipeline
#138620
passed
1 year ago
Stage: build
Stage: release
Changes
2
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test/st-KK06-algo2/potential.ml
+1
-0
1 addition, 0 deletions
test/st-KK06-algo2/potential.ml
test/st-KK06-algo2/state.ml
+3
-3
3 additions, 3 deletions
test/st-KK06-algo2/state.ml
with
4 additions
and
3 deletions
test/st-KK06-algo2/potential.ml
0 → 120000
+
1
−
0
View file @
319660d4
../
st
-
KK06
-
algo1
/
potential
.
ml
\ No newline at end of file
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test/st-KK06-algo2/state.ml
+
3
−
3
View file @
319660d4
type
t
=
int
let
to_string
=
(
fun
s
->
Printf
.
sprintf
"
f=
%i"
s
)
type
t
=
int
let
to_string
=
(
fun
s
->
Printf
.
sprintf
"%i"
s
)
let
of_string
=
Some
int_of_string
let
copy
x
=
x
let
actions
=
[
"R"
;
"R1"
]
let
potential
=
None
let
legitimate
=
None
let
fault
=
None
let
fault
=
None
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