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verimag
synchrone
sasa
Commits
28068e9f
Commit
28068e9f
authored
6 years ago
by
erwan
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New: add header to rif output
parent
7edff769
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Pipeline
#20894
passed
6 years ago
Stage: build
Changes
2
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1
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2 changed files
bin/dune
+2
-2
2 additions, 2 deletions
bin/dune
bin/sasa.ml
+2
-1
2 additions, 1 deletion
bin/sasa.ml
with
4 additions
and
3 deletions
bin/dune
+
2
−
2
View file @
28068e9f
;; Time-stamp: <modified the
2
1/0
2
/2019 (at 1
6:3
1) by Erwan Jahier>
;; Time-stamp: <modified the 1
4
/0
3
/2019 (at 1
7:0
1) by Erwan Jahier>
(executable
(name sasa)
(libraries dynlink ocamlgraph algo)
(libraries dynlink ocamlgraph algo
lutils
)
)
(install
...
...
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bin/sasa.ml
+
2
−
1
View file @
28068e9f
(* Time-stamp: <modified the 14/03/2019 (at 1
6:57
) by Erwan Jahier> *)
(* Time-stamp: <modified the 14/03/2019 (at 1
7:05
) by Erwan Jahier> *)
(* XXX Je pourrais utiliser Lwt pour rendre step non-bloquant, ce qui
permettrait d'accelerer la simu sur les machines qui ont plusieurs
...
...
@@ -179,6 +179,7 @@ let () =
exit
0
);
let
n
=
SasArg
.
args
.
length
in
if
SasArg
.
args
.
rif
then
(
Printf
.
printf
"%s"
(
Mypervasives
.
entete
"#"
"version"
"sha"
);
if
SasArg
.
args
.
demon
<>
Demon
.
Custom
then
Printf
.
printf
"#seed %i
\n
"
SasArg
.
args
.
seed
;
Printf
.
printf
"#inputs %s
\n
"
...
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