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verimag
synchrone
sasa
Commits
1a65c0c4
Commit
1a65c0c4
authored
2 years ago
by
erwan
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fix: silent configurations are necessarily legitimate
parent
12ea9fd6
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lib/sasacore/simuState.ml
+4
-3
4 additions, 3 deletions
lib/sasacore/simuState.ml
with
4 additions
and
3 deletions
lib/sasacore/simuState.ml
+
4
−
3
View file @
1a65c0c4
(* Time-stamp: <modified the 2
5
/0
1
/2023 (at 1
0:47
) by Erwan Jahier> *)
(* Time-stamp: <modified the 2
7
/0
2
/2023 (at 1
4:12
) by Erwan Jahier> *)
open
Register
open
Register
open
Topology
open
Topology
...
@@ -72,7 +72,7 @@ let update_neighbors config neighbors = StringMap.map
...
@@ -72,7 +72,7 @@ let update_neighbors config neighbors = StringMap.map
let
(
update_config
:
'
v
Conf
.
t
->
'
v
t
->
'
v
t
)
=
let
(
update_config
:
'
v
Conf
.
t
->
'
v
t
->
'
v
t
)
=
fun
e
st
->
fun
e
st
->
let
verb
=
!
Register
.
verbose_level
>
0
in
let
verb
=
!
Register
.
verbose_level
>
2
in
if
verb
then
Printf
.
eprintf
" ===> update_neighbor_env
\n
%!"
;
if
verb
then
Printf
.
eprintf
" ===> update_neighbor_env
\n
%!"
;
{
st
with
neighbors
=
update_neighbors
e
st
.
neighbors
;
config
=
e
}
{
st
with
neighbors
=
update_neighbors
e
st
.
neighbors
;
config
=
e
}
...
@@ -409,7 +409,8 @@ let (compute_potentiel: 'v t -> float) =
...
@@ -409,7 +409,8 @@ let (compute_potentiel: 'v t -> float) =
let
(
legitimate
:
'
v
t
->
bool
)
=
fun
st
->
let
(
legitimate
:
'
v
t
->
bool
)
=
fun
st
->
match
Register
.
get_legitimate
()
with
match
Register
.
get_legitimate
()
with
|
None
->
false
|
None
->
(* check if st is silent *)
get_enable_processes
st
|>
snd
|>
List
.
flatten
|>
List
.
for_all
not
|
Some
ulf
->
|
Some
ulf
->
let
pidl
=
List
.
map
(
fun
p
->
p
.
Process
.
pid
)
st
.
network
in
let
pidl
=
List
.
map
(
fun
p
->
p
.
Process
.
pid
)
st
.
network
in
ulf
pidl
(
neigbors_of_pid
st
)
ulf
pidl
(
neigbors_of_pid
st
)
...
...
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