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Created with Raphaël 2.2.030Mar2930293029282726252423222122212019201918171615141312111098767654321212128Feb272625242324232221aarch64: Add the SVE BFMLSL instructionsaarch64: Add the SME2 UZP and ZIP instructionsaarch64: Add the SME2 UNPK instructionsaarch64: Add the SME2 shift instructionsaarch64: Add the SME2 saturating conversion instructionsaarch64: Add the SME2 FP<->FP conversion instructionsaarch64: Add the SME2 FP<->int conversion instructionsaarch64: Add the SME2 CLAMP instructionsaarch64: Add the SME2 MOPA and MOPS instructionsaarch64: Add the SME2 vertical dot-product instructionsaarch64: Add the SME2 dot-product instructionsaarch64: Add the SME2 MLALL and MLSLL instructionsaarch64: Add the SME2 MLAL and MLSL instructionsaarch64: Add the SME2 FMLA and FMLS instructionsaarch64: Add the SME2 maximum/minimum instructionsaarch64: Add the SME2 ADD and SUB instructionsaarch64: Add the SME2 ZT0 instructionsaarch64: Add the SME2 predicate-related instructionsaarch64: Add the SME2 multivector LD1 and ST1 instructionsaarch64: Add the SME2 MOVA instructionsaarch64: Add support for predicate-as-counter registersaarch64; Add support for vector offset rangesaarch64: Add support for vgx2 and vgx4aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayaarch64: Add a _10 suffix to FLD_imm3aarch64: Add +sme2aarch64: Prefer register ranges & support wrappingaarch64: Add support for strided register listsaarch64: Sort fields alphanumericallyaarch64: Resync field namesaarch64: Regularise FLD_* suffixesaarch64: Rename some of GAS's REG_TYPE_* macrosaarch64: Add a aarch64_cpu_supports_inst_p helperaarch64: Reorder some OP_SVE_* macrosaarch64: Rename aarch64-tbl.h OP_SME_* macrosaarch64: Tweak priorities of parsing-related errorsaarch64: Try to report invalid variants against the closest matchaarch64: Tweak register list errorsaarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldaarch64: Add an operand class for SVE register lists