Commits · 642a97391ae81d6a774aae651889501e4e840f0e · Sebastien Michelland / binutils-gdb

May 06, 2021

or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha() · 0b3e14c9

Stafford Horne authored 3 years ago

The gotha() relocation mnemonic will be outputted by OpenRISC GCC when
using the -mcmodel=large option.  This relocation is used along with
got() to generate 32-bit GOT offsets.  This increases the previous GOT
offset limit from the previous 16-bit (64K) limit.

This is needed on large binaries where the GOT grows larger than 64k.

bfd/ChangeLog:

	PR 21464
	* bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation.
	* elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise.
	(or1k_final_link_relocate, or1k_elf_relocate_section,
	or1k_elf_check_relocs): Likewise.
	* libbfd.h (bfd_reloc_code_real_names): Likewise.
	* reloc.c: Likewise.

cpu/ChangeLog:

	PR 21464
	* or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic
	for gotha() relocation.

include/ChangeLog:

	PR 21464
	* elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number.

opcodes/ChangeLog:

	PR 21464
	* or1k-asm.c: Regenerate.

gas/ChangeLog:

	PR 21464
	* testsuite/gas/or1k/reloc-1.s: Add test for new relocation.
	* testsuite/gas/or1k/reloc-1.d: Add test result for new
	relocation.

Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>

fixup reloc, add tests

0b3e14c9

Jun 12, 2019

cpu/or1k: Add support for orfp64a32 spec · 6ce26ac7

Stafford Horne authored 5 years ago

This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by
using register pairs.  The functionality has been added to OpenRISC architecture
specification version 1.3 as per architecture proposal 14[0].

For supporting assembly of both 64-bit and 32-bit precision instructions we have
defined CGEN_VALIDATE_INSN_SUPPORTED.  This allows cgen to use 64-bit bit
architecture assembly parsing on 64-bit toolchains and 32-bit architecture
assembly parsing on 32-bit toolchains.  Without this the assembler has issues
parsing register pairs.

This patch also contains a few fixes to the symantics for existing OpenRISC
single and double precision FPU operations.

[0] https://openrisc.io/proposals/orfpx64a32

cpu/ChangeLog:

yyyy-mm-dd  Andrey Bacherov  <avbacherov@opencores.org>
	    Stafford Horne  <shorne@gmail.com>

	* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
	(ORFPX-MACHS): Removed pmacro.
	* or1k.opc (or1k_cgen_insn_supported): New function.
	(CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
	(parse_regpair, print_regpair): New functions.
	* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
	and add comments.
	(h-fdr): Update comment to indicate or64.
	(reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
	(h-fd32r): New hardware for 64-bit fpu registers.
	(h-i64r): New hardware for 64-bit int registers.
	* or1korbis.cpu (f-resv-8-1): New field.
	* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
	(rDDF, rADF, rBDF): Update operand comment to indicate or64.
	(f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
	(h-roff1): New hardware.
	(double-field-and-ops mnemonic): New pmacro to generate operations
	rDD32F, rAD32F, rBD32F, rDDI and rADI.
	(float-regreg-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(float-setflag-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Fix double instructions from single to double
	precision.  Add generator for or32 64-bit instructions.
	(float-cust-insn cust-num): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
	ORFPX32-MACHS.
	(lf-rem-d): Fix operation from mod to rem.
	(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
	(lf-itof-d): Fix operands from single to double.
	(lf-ftoi-d): Update operand mode from DI to WI.

6ce26ac7

Oct 05, 2018

or1k: Add the l.adrp insn and supporting relocations · c8e98e36

Stafford Horne authored 6 years ago

This patch adds the new instruction and relocation as per proposal:
   https://openrisc.io/proposals/ladrp

This is to be added to the spec in an upcoming revision.  The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits.  This is meant to be used with
a 13-bit lower bit page offset.  This allows us to free up the got
register r16.

  l.adrp  r3, foo
  l.ori   r4, r3, po(foo)
  l.lbz   r5, po(foo)(r3)
  l.sb    po(foo)(r3), r6

The relocations we add are:

 - BFD_RELOC_OR1K_PLTA26	For PLT jump relocation with PLT entry
   asm: plta()			implemented using l.ardp, meaning
				no need for r16 (the GOT reg)

 - BFD_RELOC_OR1K_GOT_PG21	Upper 21-bit Page offset got address
   asm: got()
 - BFD_RELOC_OR1K_TLS_GD_PG21	Upper 21-bit Page offset with TLS General
   asm: tlsgd()			Dynamic calculation
 - BFD_RELOC_OR1K_TLS_LDM_PG21	Upper 21-bit Page offset with TLS local
   asm: tlsldm()		dynamic calculation
 - BFD_RELOC_OR1K_TLS_IE_PG21	Upper 21-bit Page offset with TLS Initial
   asm: gottp() 		Executable calculation
 - BFD_RELOC_OR1K_PCREL_PG21	Default relocation for disp21 (l.adrp
				instructions)

 - BFD_RELOC_OR1K_LO13		low 13-bit page offset relocation
   asm: po()			i.e. mem loads, addi etc
 - BFD_RELOC_OR1K_SLO13		low 13-bit page offset relocation
   asm: po()			i.e. mem stores, with split immediate
 - BFD_RELOC_OR1K_GOT_LO13,	low 13-bit page offset with GOT calcs
   asm: gotpo()
 - BFD_RELOC_OR1K_TLS_GD_LO13	Lower 13-bit offset with TLS GD calcs
   asm: tlsgdpo()
 - BFD_RELOC_OR1K_TLS_LDM_LO13	Lower 13-bit offset with TLS LD calcs
   asm: tlsldmpo()
 - BFD_RELOC_OR1K_TLS_IE_LO13	Lower 13-bit offset with TLS IE calcs
   asm: gottppo()

bfd/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* bfd-in2.h: Regenerated.
	* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
	R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
	R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
	R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
	R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
	(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
	BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
	BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
	BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
	BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
	BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
	BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
	(elf_or1k_link_hash_table): Add field saw_plta.
	(or1k_final_link_relocate): Add value calculations for new relocations.
	(or1k_elf_relocate_section): Add section relocations for new
	relocations.
	(or1k_write_plt_entry): New function.
	(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
	using new l.adrp instruction.  Cleanup PLT relocation code generation.
	* libbfd.h: Regenerated.
	* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
	BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
	BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
	BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
	BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
	BFD_RELOC_OR1K_TLS_IE_LO13.

cpu/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k.opc (parse_disp26): Add support for plta() relocations.
	(parse_disp21): New function.
	(or1k_rclass): New enum.
	(or1k_rtype): New enum.
	(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
	(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
	(parse_imm16): Add support for the new 21bit and 13bit relocations.
	* or1korbis.cpu (f-disp26): Don't assume SI.
	(f-disp21): New pc-relative 21-bit 13 shifted to right.
	(insn-opcode): Add ADRP.
	(l-adrp): New instruction.

gas/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
	BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
	BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
	BFD_RELOC_OR1K_TLS_IE_LO13.
	* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
	* testsuite/gas/or1k/allinsn.d: Add test results for new
	instructions.
	* testsuite/gas/or1k/reloc-1.s: Add tests to generate
	R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
	R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
	R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
	relocations.
	* testsuite/gas/or1k/reloc-1.d: Add relocation results for
	tests.
	* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
	gotpo().
	* testsuite/gas/or1k/reloc-2.l: Add expected error test results.

ld/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
	* testsuite/ld-or1k/plt1.dd: New file.
	* testsuite/ld-or1k/plt1.s: New file.
	* testsuite/ld-or1k/plt1.x.dd: New file.
	* testsuite/ld-or1k/plta1.dd: New file.
	* testsuite/ld-or1k/plta1.s: New file.
	* testsuite/ld-or1k/pltlib.s: New file.

include/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
	R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
	R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
	R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
	R_OR1K_SLO13, R_OR1K_PLTA26.

opcodes/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k-asm.c: Regenerated.
	* or1k-desc.c: Regenerated.
	* or1k-desc.h: Regenerated.
	* or1k-dis.c: Regenerated.
	* or1k-ibld.c: Regenerated.
	* or1k-opc.c: Regenerated.
	* or1k-opc.h: Regenerated.
	* or1k-opinst.c: Regenerated.

c8e98e36

or1k: Add relocations for high-signed and low-stores · 1c4f3780

Richard Henderson authored 6 years ago

This patch adds the following target relocations:

 - BFD_RELOC_HI16_S		High 16-bit relocation, for used with signed
   asm: ha()			lower.
 - BFD_RELOC_HI16_S_GOTOFF	High 16-bit GOT offset relocation for local
   asm: gotoffha()		symbols, for use with signed lower.
 - BFD_RELOC_OR1K_TLS_IE_AHI16	High 16-bit TLS relocation with initial
   asm: gottpoffha()		executable calculation, for use with signed
				lower.
 - BFD_RELOC_OR1K_TLS_LE_AHI16	High 16-bit TLS relocation for local executable
   asm: tpoffha()		variables, for use with signed lower.

 - BFD_RELOC_OR1K_SLO16		Split lower 16-bit relocation, used with
   asm: lo()			OpenRISC store instructions.
 - BFD_RELOC_OR1K_GOTOFF_SLO16	Split lower 16-bit GOT offset relocation for
   asm: gotofflo()		local symbols, used with OpenRISC store
				instructions.
 - BFD_RELOC_OR1K_TLS_LE_SLO16	Split lower 16-bit relocation for TLS local
   asm: tpofflo()		executable variables, used with OpenRISC store
				instructions.

bfd/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>
	    Stafford Horne  <shorne@gmail.com>

	* bfd-in2.h: Regenerated.
	* elf32-or1k.c (N_ONES): New macro.
	(or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow.
	Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF,
	R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16,
	R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16,
	R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
	(or1k_reloc_map): Add entries for BFD_RELOC_HI16_S,
	BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF,
	BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
	BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16,
	BFD_RELOC_OR1K_TLS_LE_SLO16.
	(or1k_reloc_type_lookup): Change search loop to start ad index 0 and
	also check results before returning.
	(or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index
	limit.
	(or1k_final_link_relocate): New function.
	(or1k_elf_relocate_section): Add support for new AHI and SLO
	relocations.  Use or1k_final_link_relocate instead of generic
	_bfd_final_link_relocate.
	(or1k_elf_check_relocs): Add support for new AHI and SLO relocations.
	* reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16,
	BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16,
	BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
	BFD_RELOC_OR1K_TLS_LE_SLO16.  Remove unused BFD_RELOC_OR1K_GOTOFF_HI16
	and BFD_RELOC_OR1K_GOTOFF_LO16.
	* libbfd.h: Regenerated.

cpu/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k.opc: Add RTYPE_ enum.
	(INVALID_STORE_RELOC): New string.
	(or1k_imm16_relocs): New array array.
	(parse_reloc): New static function that just does the parsing.
	(parse_imm16): New static function for generic parsing.
	(parse_simm16): Change to just call parse_imm16.
	(parse_simm16_split): New function.
	(parse_uimm16): Change to call parse_imm16.
	(parse_uimm16_split): New function.
	* or1korbis.cpu (simm16-split): Change to use new simm16_split.
	(uimm16-split): Change to use new uimm16_split.

gas/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation.
	* testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations.
	* testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp.
	* testsuite/gas/or1k/or1k.exp: Add reloc-2 list test.
	* testsuite/gas/or1k/reloc-1.d: New file.
	* testsuite/gas/or1k/reloc-1.s: New file.
	* testsuite/gas/or1k/reloc-2.l: New file.
	* testsuite/gas/or1k/reloc-2.s: New file.

include/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
	R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
	R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.

ld/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* testsuite/ld-or1k/offsets1.d: New file.
	* testsuite/ld-or1k/offsets1.s: New file.
	* testsuite/ld-or1k/or1k.exp: New file.

opcodes/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k-asm.c: Regenerate.

1c4f3780

Jun 12, 2014
- Whitespace fixes for cpu/or1k.opc · c151b1c6
  Alan Modra authored 10 years ago
  
  * or1k.opc: Whitespace fixes.
  c151b1c6
Apr 22, 2014
- Remove support for the (deprecated) openrisc and or32 configurations and replace · 73589c9d
  Christian Svensson authored 10 years ago
  
  with support for the new or1k configuration.
  73589c9d