Reported by Rich Felker when building on 32-bit hosts.  Backwards jump
negative offsets were not calculated correctly due to improper 32-bit
to 64-bit zero-extension.  The 64-bit fields are present because we
are mixing 32-bit and 64-bit architectures in our cpu descriptions.

Removing 64-bit fixes the issue.  We don't use 64-bit, there is an architecture
spec for 64-bit but no implementations or simulators.  My thought is if
we need them in the future we should do the proper work to support both
32-bit and 64-bit implementations co-existing then.

cpu/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	PR 25184
	* or1k.cpu (arch or1k): Remove or64 and or64nd machs.
	(ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
	(cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
	* or1kcommon.cpu (h-fdr): Remove hardware.
	* or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
	(float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
	(float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
	(float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
	(lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.

The 'nd' architectures did not mention what the 'nd' stands for.
Document that these mean 'no brach delay slot'.

cpu/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a
	(l-adrp): Improve comment.

This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by
using register pairs.  The functionality has been added to OpenRISC architecture
specification version 1.3 as per architecture proposal 14[0].

For supporting assembly of both 64-bit and 32-bit precision instructions we have
defined CGEN_VALIDATE_INSN_SUPPORTED.  This allows cgen to use 64-bit bit
architecture assembly parsing on 64-bit toolchains and 32-bit architecture
assembly parsing on 32-bit toolchains.  Without this the assembler has issues
parsing register pairs.

This patch also contains a few fixes to the symantics for existing OpenRISC
single and double precision FPU operations.

[0] https://openrisc.io/proposals/orfpx64a32

cpu/ChangeLog:

yyyy-mm-dd  Andrey Bacherov  <avbacherov@opencores.org>
	    Stafford Horne  <shorne@gmail.com>

	* or1k.cpu (ORFPX64A32-MACHS): New pmacro.
	(ORFPX-MACHS): Removed pmacro.
	* or1k.opc (or1k_cgen_insn_supported): New function.
	(CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
	(parse_regpair, print_regpair): New functions.
	* or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
	and add comments.
	(h-fdr): Update comment to indicate or64.
	(reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
	(h-fd32r): New hardware for 64-bit fpu registers.
	(h-i64r): New hardware for 64-bit int registers.
	* or1korbis.cpu (f-resv-8-1): New field.
	* or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
	(rDDF, rADF, rBDF): Update operand comment to indicate or64.
	(f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
	(h-roff1): New hardware.
	(double-field-and-ops mnemonic): New pmacro to generate operations
	rDD32F, rAD32F, rBD32F, rDDI and rADI.
	(float-regreg-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(float-setflag-insn): Update single precision generator to MACH
	ORFPX32-MACHS.  Fix double instructions from single to double
	precision.  Add generator for or32 64-bit instructions.
	(float-cust-insn cust-num): Update single precision generator to MACH
	ORFPX32-MACHS.  Add generator for or32 64-bit instructions.
	(lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
	ORFPX32-MACHS.
	(lf-rem-d): Fix operation from mod to rem.
	(lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
	(lf-itof-d): Fix operands from single to double.
	(lf-ftoi-d): Update operand mode from DI to WI.

with support for the new or1k configuration.