Move cpu files from cgen/cpu to top level cpu directory.

cpu/ChangeLog

+2011-08-22  Nick Clifton  <nickc@redhat.com>
+
+	* fr30.cpu: Newly contributed file.
+	* fr30.opc: Likewise.
+	* ip2k.cpu: Likewise.
+	* ip2k.opc: Likewise.
+	* mep-avc.cpu: Likewise.
+	* mep-avc2.cpu: Likewise.
+	* mep-c5.cpu: Likewise.
+	* mep-core.cpu: Likewise.
+	* mep-default.cpu: Likewise.
+	* mep-ext-cop.cpu: Likewise.
+	* mep-fmax.cpu: Likewise.
+	* mep-h1.cpu: Likewise.
+	* mep-ivc2.cpu: Likewise.
+	* mep-rhcop.cpu: Likewise.
+	* mep-sample-ucidsp.cpu: Likewise.
+	* mep.cpu: Likewise.
+	* mep.opc: Likewise.
+	* openrisc.cpu: Likewise.
+	* openrisc.opc: Likewise.
+	* xstormy16.cpu: Likewise.
+	* xstormy16.opc: Likewise.
+
 2010-10-08  Pierre Muller  <muller@ics.u-strasbg.fr>
 
 	* frv.opc: #undef DEBUG.

cpu/fr30.opc

+/* FR30 opcode support.  -*- C -*-
+   Copyright 2011 Free Software Foundation, Inc.
+
+   Contributed by Red Hat Inc;
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file is an addendum to fr30.cpu.  Heavy use of C code isn't
+   appropriate in .cpu files, so it resides here.  This especially applies
+   to assembly/disassembly where parsing/printing can be quite involved.
+   Such things aren't really part of the specification of the cpu, per se,
+   so .cpu files provide the general framework and .opc files handle the
+   nitty-gritty details as necessary.
+
+   Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h".  */
+
+/* -- opc.h */
+
+/* ??? This can be improved upon.  */
+#undef  CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 16
+#undef  CGEN_DIS_HASH
+#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4)
+
+/* -- */
+
+/* -- asm.c */
+/* Handle register lists for LDMx and STMx.  */
+
+static int
+parse_register_number (const char **strp)
+{
+  int regno;
+
+  if (**strp < '0' || **strp > '9')
+    return -1; /* Error.  */
+  regno = **strp - '0';
+  ++*strp;
+
+  if (**strp >= '0' && **strp <= '9')
+    {
+      regno = regno * 10 + (**strp - '0');
+      ++*strp;
+    }
+
+  return regno;
+}
+
+static const char *
+parse_register_list (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		     const char **strp,
+		     int opindex ATTRIBUTE_UNUSED,
+		     unsigned long *valuep,
+		     int high_low,   /* 0 == high, 1 == low.  */
+		     int load_store) /* 0 == load, 1 == store.  */
+{
+  *valuep = 0;
+  while (**strp && **strp != ')')
+    {
+      int regno;
+
+      if (**strp != 'R' && **strp != 'r')
+	break;
+      ++*strp;
+
+      regno = parse_register_number (strp);
+      if (regno == -1)
+	return _("Register number is not valid");
+      if (regno > 7 && !high_low)
+	return _("Register must be between r0 and r7");
+      if (regno < 8 && high_low)
+	return _("Register must be between r8 and r15");
+
+      if (high_low)
+	regno -= 8;
+
+      if (load_store) /* Mask is reversed for store.  */
+	*valuep |= 0x80 >> regno;
+      else
+	*valuep |= 1 << regno;
+
+      if (**strp == ',')
+	{
+	  if (*(*strp + 1) == ')')
+	    break;
+	  ++*strp;
+	}
+    }
+
+  if (!*strp || **strp != ')')
+    return _("Register list is not valid");
+
+  return NULL;
+}
+
+static const char *
+parse_low_register_list_ld (CGEN_CPU_DESC cd,
+			    const char **strp,
+			    int opindex,
+			    unsigned long *valuep)
+{
+  return parse_register_list (cd, strp, opindex, valuep,
+			      0 /* Low.  */, 0 /* Load.  */);
+}
+
+static const char *
+parse_hi_register_list_ld (CGEN_CPU_DESC cd,
+			   const char **strp,
+			   int opindex,
+			   unsigned long *valuep)
+{
+  return parse_register_list (cd, strp, opindex, valuep,
+			      1 /* High.  */, 0 /* Load.  */);
+}
+
+static const char *
+parse_low_register_list_st (CGEN_CPU_DESC cd,
+			    const char **strp,
+			    int opindex,
+			    unsigned long *valuep)
+{
+  return parse_register_list (cd, strp, opindex, valuep,
+			      0 /* Low.  */, 1 /* Store.  */);
+}
+
+static const char *
+parse_hi_register_list_st (CGEN_CPU_DESC cd,
+			   const char **strp,
+			   int opindex,
+			   unsigned long *valuep)
+{
+  return parse_register_list (cd, strp, opindex, valuep,
+			      1 /* High.  */, 1 /* Store.  */);
+}
+
+/* -- */
+
+/* -- dis.c */
+static void
+print_register_list (void * dis_info,
+		     long value,
+		     long offset,
+		     int load_store) /* 0 == load, 1 == store.  */
+{
+  disassemble_info *info = dis_info;
+  int mask;
+  int reg_index = 0;
+  char * comma = "";
+
+  if (load_store)
+    mask = 0x80;
+  else
+    mask = 1;
+
+  if (value & mask)
+    {
+      (*info->fprintf_func) (info->stream, "r%li", reg_index + offset);
+      comma = ",";
+    }
+    
+  for (reg_index = 1; reg_index <= 7; ++reg_index)
+    {
+      if (load_store)
+	mask >>= 1;
+      else
+	mask <<= 1;
+
+      if (value & mask)
+	{
+	  (*info->fprintf_func) (info->stream, "%sr%li", comma, reg_index + offset);
+	  comma = ",";
+	}
+    }
+}
+
+static void
+print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			   void * dis_info,
+			   long value,
+			   unsigned int attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc ATTRIBUTE_UNUSED,
+			   int length ATTRIBUTE_UNUSED)
+{
+  print_register_list (dis_info, value, 8, 0 /* Load.  */);
+}
+
+static void
+print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			    void * dis_info,
+			    long value,
+			    unsigned int attrs ATTRIBUTE_UNUSED,
+			    bfd_vma pc ATTRIBUTE_UNUSED,
+			    int length ATTRIBUTE_UNUSED)
+{
+  print_register_list (dis_info, value, 0, 0 /* Load.  */);
+}
+
+static void
+print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			   void * dis_info,
+			   long value,
+			   unsigned int attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc ATTRIBUTE_UNUSED,
+			   int length ATTRIBUTE_UNUSED)
+{
+  print_register_list (dis_info, value, 8, 1 /* Store.  */);
+}
+
+static void
+print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			    void * dis_info,
+			    long value,
+			    unsigned int attrs ATTRIBUTE_UNUSED,
+			    bfd_vma pc ATTRIBUTE_UNUSED,
+			    int length ATTRIBUTE_UNUSED)
+{
+  print_register_list (dis_info, value, 0, 1 /* Store.  */);
+}
+
+static void
+print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	  void * dis_info,
+	  long value,
+	  unsigned int attrs ATTRIBUTE_UNUSED,
+	  bfd_vma pc ATTRIBUTE_UNUSED,
+	  int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  (*info->fprintf_func) (info->stream, "%ld", value);
+}
+/* -- */

cpu/ip2k.opc

+/* IP2K opcode support.  -*- C -*-
+   Copyright 2002, 2005, 2011 Free Software Foundation, Inc.
+
+   Contributed by Red Hat Inc;
+
+   This file is part of the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/*
+   Each section is delimited with start and end markers.
+
+   <arch>-opc.h additions use: "-- opc.h"
+   <arch>-opc.c additions use: "-- opc.c"
+   <arch>-asm.c additions use: "-- asm.c"
+   <arch>-dis.c additions use: "-- dis.c"
+   <arch>-ibd.h additions use: "-- ibd.h".  */
+
+/* -- opc.h */
+
+/* Check applicability of instructions against machines.  */
+#define CGEN_VALIDATE_INSN_SUPPORTED
+
+/* Allows reason codes to be output when assembler errors occur.  */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* Override disassembly hashing - there are variable bits in the top
+   byte of these instructions.  */
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf, value) \
+  (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
+
+#define CGEN_ASM_HASH_SIZE 127
+#define CGEN_ASM_HASH(insn) ip2k_asm_hash (insn)
+
+extern unsigned int ip2k_asm_hash (const char *);
+extern int ip2k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+
+/* -- opc.c */
+
+#include "safe-ctype.h"
+
+/* A better hash function for instruction mnemonics.  */
+unsigned int
+ip2k_asm_hash (const char* insn)
+{
+  unsigned int hash;
+  const char* m = insn;
+
+  for (hash = 0; *m && ! ISSPACE (*m); m++)
+    hash = (hash * 23) ^ (0x1F & TOLOWER (*m));
+
+  /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
+
+  return hash % CGEN_ASM_HASH_SIZE;
+}
+
+
+/* Special check to ensure that instruction exists for given machine.  */
+
+int
+ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+  int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
+
+  /* No mach attribute?  Assume it's supported for all machs.  */
+  if (machs == 0)
+    return 1;
+  
+  return (machs & cd->machs) != 0;
+}
+
+
+/* -- asm.c */
+
+static const char *
+parse_fr (CGEN_CPU_DESC cd,
+	  const char **strp,
+	  int opindex,
+	  unsigned long *valuep)
+{
+  const char *errmsg;
+  const char *old_strp;
+  char *afteroffset; 
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+  extern CGEN_KEYWORD ip2k_cgen_opval_register_names;
+  bfd_vma tempvalue;
+
+  old_strp = *strp;
+  afteroffset = NULL;
+
+  /* Check here to see if you're about to try parsing a w as the first arg
+     and return an error if you are.  */
+  if ((strncmp (*strp, "w", 1) == 0) || (strncmp (*strp, "W", 1) == 0))
+    {
+      (*strp)++;
+
+      if ((strncmp (*strp, ",", 1) == 0) || ISSPACE (**strp))
+	{
+	  /* We've been passed a w.  Return with an error message so that
+	     cgen will try the next parsing option.  */
+	  errmsg = _("W keyword invalid in FR operand slot.");
+	  return errmsg;
+	}
+      *strp = old_strp;
+    }
+
+  /* Attempt parse as register keyword. */
+  errmsg = cgen_parse_keyword (cd, strp, & ip2k_cgen_opval_register_names,
+			       (long *) valuep);
+  if (*strp != NULL
+      && errmsg == NULL)
+    return errmsg;
+
+  /* Attempt to parse for "(IP)".  */
+  afteroffset = strstr (*strp, "(IP)");
+
+  if (afteroffset == NULL)
+    /* Make sure it's not in lower case.  */
+    afteroffset = strstr (*strp, "(ip)");
+
+  if (afteroffset != NULL)
+    {
+      if (afteroffset != *strp)
+	{
+	  /* Invalid offset present.  */
+	  errmsg = _("offset(IP) is not a valid form");
+	  return errmsg;
+	}
+      else
+	{
+	  *strp += 4; 
+	  *valuep = 0;
+	  errmsg = NULL;
+	  return errmsg;
+	}
+    }
+
+  /* Attempt to parse for DP. ex: mov w, offset(DP)
+                                  mov offset(DP),w   */
+
+  /* Try parsing it as an address and see what comes back.  */
+  afteroffset = strstr (*strp, "(DP)");
+
+  if (afteroffset == NULL)
+    /* Maybe it's in lower case.  */
+    afteroffset = strstr (*strp, "(dp)");
+
+  if (afteroffset != NULL)
+    {
+      if (afteroffset == *strp)
+	{
+	  /* No offset present. Use 0 by default.  */
+	  tempvalue = 0;
+	  errmsg = NULL;
+	}
+      else
+	errmsg = cgen_parse_address (cd, strp, opindex,
+				     BFD_RELOC_IP2K_FR_OFFSET,
+				     & result_type, & tempvalue);
+
+      if (errmsg == NULL)
+	{
+	  if (tempvalue <= 127)
+	    {
+	      /* Value is ok.  Fix up the first 2 bits and return.  */
+	      *valuep = 0x0100 | tempvalue;
+	      *strp += 4; /* Skip over the (DP) in *strp.  */
+	      return errmsg;
+	    }
+	  else
+	    {
+	      /* Found something there in front of (DP) but it's out
+		 of range.  */
+	      errmsg = _("(DP) offset out of range.");
+	      return errmsg;
+	    }
+	}
+    }
+
+
+  /* Attempt to parse for SP. ex: mov w, offset(SP)
+                                  mov offset(SP), w.  */
+  afteroffset = strstr (*strp, "(SP)");
+
+  if (afteroffset == NULL)
+    /* Maybe it's in lower case.  */
+    afteroffset = strstr (*strp, "(sp)");
+
+  if (afteroffset != NULL)
+    {
+      if (afteroffset == *strp)
+	{
+	  /* No offset present. Use 0 by default.  */
+	  tempvalue = 0;
+	  errmsg = NULL;
+	}
+      else
+	errmsg = cgen_parse_address (cd, strp, opindex,
+				     BFD_RELOC_IP2K_FR_OFFSET,
+				     & result_type, & tempvalue);
+
+      if (errmsg == NULL)
+	{
+	  if (tempvalue <= 127)
+	    {
+	      /* Value is ok.  Fix up the first 2 bits and return.  */
+	      *valuep = 0x0180 | tempvalue;
+	      *strp += 4; /* Skip over the (SP) in *strp.  */
+	      return errmsg;
+	    }
+	  else
+	    {
+	      /* Found something there in front of (SP) but it's out
+		 of range.  */
+	      errmsg = _("(SP) offset out of range.");
+	      return errmsg;
+	    }
+	}
+    }
+
+  /* Attempt to parse as an address.  */
+  *strp = old_strp;
+  errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR9,
+			       & result_type, & value);
+  if (errmsg == NULL)
+    {
+      *valuep = value;
+
+      /* If a parenthesis is found, warn about invalid form.  */
+      if (**strp == '(')
+	errmsg = _("illegal use of parentheses");
+
+      /* If a numeric value is specified, ensure that it is between
+	 1 and 255.  */
+      else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  if (value < 0x1 || value > 0xff)
+	    errmsg = _("operand out of range (not between 1 and 255)");
+	}
+    }
+  return errmsg;
+}
+
+static const char *
+parse_addr16 (CGEN_CPU_DESC cd,
+	      const char **strp,
+	      int opindex,
+	      unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+  bfd_vma value;
+
+  if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16H)
+    code = BFD_RELOC_IP2K_HI8DATA;
+  else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16L)
+    code = BFD_RELOC_IP2K_LO8DATA;
+  else
+    {
+      /* Something is very wrong. opindex has to be one of the above.  */
+      errmsg = _("parse_addr16: invalid opindex.");
+      return errmsg;
+    }
+  
+  errmsg = cgen_parse_address (cd, strp, opindex, code,
+			       & result_type, & value);
+  if (errmsg == NULL)
+    {
+      /* We either have a relocation or a number now.  */
+      if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  /* We got a number back.  */
+	  if (code == BFD_RELOC_IP2K_HI8DATA)
+            value >>= 8;
+	  else
+	    /* code = BFD_RELOC_IP2K_LOW8DATA.  */
+	    value &= 0x00FF;
+	}   
+      *valuep = value;
+    }
+
+  return errmsg;
+}
+
+static const char *
+parse_addr16_cjp (CGEN_CPU_DESC cd,
+		  const char **strp,
+		  int opindex,
+		  unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+  bfd_vma value;
+ 
+  if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP)
+    code = BFD_RELOC_IP2K_ADDR16CJP;
+  else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P)
+    code = BFD_RELOC_IP2K_PAGE3;
+
+  errmsg = cgen_parse_address (cd, strp, opindex, code,
+			       & result_type, & value);
+  if (errmsg == NULL)
+    {
+      if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  if ((value & 0x1) == 0)  /* If the address is even .... */
+	    {
+	      if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP)
+                *valuep = (value >> 1) & 0x1FFF;  /* Should mask be 1FFF?  */
+	      else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P)
+                *valuep = (value >> 14) & 0x7;
+	    }
+          else
+ 	    errmsg = _("Byte address required. - must be even.");
+	}
+      else if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED)
+	{
+	  /* This will happen for things like (s2-s1) where s2 and s1
+	     are labels.  */
+	  *valuep = value;
+	}
+      else 
+        errmsg = _("cgen_parse_address returned a symbol. Literal required.");
+    }
+  return errmsg; 
+}
+
+static const char *
+parse_lit8 (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_reloc_code_real_type code = BFD_RELOC_NONE;
+  bfd_vma value;
+
+  /* Parse %OP relocating operators.  */
+  if (strncmp (*strp, "%bank", 5) == 0)
+    {
+      *strp += 5;
+      code = BFD_RELOC_IP2K_BANK;
+    }
+  else if (strncmp (*strp, "%lo8data", 8) == 0)
+    {
+      *strp += 8;
+      code = BFD_RELOC_IP2K_LO8DATA;
+    }
+  else if (strncmp (*strp, "%hi8data", 8) == 0)
+    {
+      *strp += 8;
+      code = BFD_RELOC_IP2K_HI8DATA;
+    }
+  else if (strncmp (*strp, "%ex8data", 8) == 0)
+    {
+      *strp += 8;
+      code = BFD_RELOC_IP2K_EX8DATA;
+    }
+  else if (strncmp (*strp, "%lo8insn", 8) == 0)
+    {
+      *strp += 8;
+      code = BFD_RELOC_IP2K_LO8INSN;
+    }
+  else if (strncmp (*strp, "%hi8insn", 8) == 0)
+    {
+      *strp += 8;
+      code = BFD_RELOC_IP2K_HI8INSN;
+    }
+
+  /* Parse %op operand.  */
+  if (code != BFD_RELOC_NONE)
+    {
+      errmsg = cgen_parse_address (cd, strp, opindex, code, 
+				   & result_type, & value);
+      if ((errmsg == NULL) &&
+	  (result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED))
+	errmsg = _("percent-operator operand is not a symbol");
+
+      *valuep = value;
+    }
+  /* Parse as a number.  */
+  else
+    {
+      errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
+
+      /* Truncate to eight bits to accept both signed and unsigned input.  */
+      if (errmsg == NULL)
+	*valuep &= 0xFF;
+    }
+
+  return errmsg;
+}
+
+static const char *
+parse_bit3 (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    unsigned long *valuep)
+{
+  const char *errmsg;
+  char mode = 0;
+  long count = 0;
+  unsigned long value;
+
+  if (strncmp (*strp, "%bit", 4) == 0)
+    {
+      *strp += 4;
+      mode = 1;
+    }
+  else if (strncmp (*strp, "%msbbit", 7) == 0)
+    {
+      *strp += 7;
+      mode = 1;
+    }
+  else if (strncmp (*strp, "%lsbbit", 7) == 0)
+    {
+      *strp += 7;
+      mode = 2;
+    }
+
+  errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+  if (errmsg)
+    return errmsg;
+
+  if (mode)
+    {
+      value = * valuep;
+      if (value == 0)
+	{
+	  errmsg = _("Attempt to find bit index of 0");
+	  return errmsg;
+	}
+    
+      if (mode == 1)
+	{
+	  count = 31;
+	  while ((value & 0x80000000) == 0)
+	    {
+	      count--;
+	      value <<= 1;
+	    }
+	}
+      else if (mode == 2)
+	{
+	  count = 0;
+	  while ((value & 0x00000001) == 0)
+	    {
+	      count++;
+	      value >>= 1;
+	    }
+	}
+    
+      *valuep = count;
+    }
+
+  return errmsg;
+}
+
+/* -- dis.c */
+
+static void
+print_fr (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	  void * dis_info,
+	  long value,
+	  unsigned int attrs ATTRIBUTE_UNUSED,
+	  bfd_vma pc ATTRIBUTE_UNUSED,
+	  int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  const CGEN_KEYWORD_ENTRY *ke;
+  extern CGEN_KEYWORD ip2k_cgen_opval_register_names;
+  long offsettest;
+  long offsetvalue;
+
+  if (value == 0) /* This is (IP).  */
+    {
+      (*info->fprintf_func) (info->stream, "%s", "(IP)");
+      return;
+    }
+
+  offsettest = value >> 7;
+  offsetvalue = value & 0x7F;
+
+  /* Check to see if first two bits are 10 -> (DP).  */
+  if (offsettest == 2)
+    {
+      if (offsetvalue == 0)
+	(*info->fprintf_func) (info->stream, "%s","(DP)");
+      else
+	(*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue, "(DP)");
+      return;
+    }
+
+  /* Check to see if first two bits are 11 -> (SP).  */
+  if (offsettest == 3)
+    {
+      if (offsetvalue == 0)
+	(*info->fprintf_func) (info->stream, "%s", "(SP)");
+      else
+	(*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue,"(SP)");
+      return;
+    }
+
+  /* Attempt to print as a register keyword.  */
+  ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value);
+
+  if (ke != NULL)
+    (*info->fprintf_func) (info->stream, "%s", ke->name);
+  else
+    /* Print as an address literal.  */
+    (*info->fprintf_func) (info->stream, "$%02lx", value);
+}
+
+static void
+print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		 void * dis_info,
+		 long value,
+		 unsigned int attrs ATTRIBUTE_UNUSED,
+		 bfd_vma pc ATTRIBUTE_UNUSED,
+		 int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  (*info->fprintf_func) (info->stream, "$%lx", value);
+}
+
+static void
+print_dollarhex8 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		  void * dis_info,
+		  long value,
+		  unsigned int attrs ATTRIBUTE_UNUSED,
+		  bfd_vma pc ATTRIBUTE_UNUSED,
+		  int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  (*info->fprintf_func) (info->stream, "$%02lx", value);
+}
+
+static void
+print_dollarhex_addr16h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			 void * dis_info,
+			 long value,
+			 unsigned int attrs ATTRIBUTE_UNUSED,
+			 bfd_vma pc ATTRIBUTE_UNUSED,
+			 int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  /* This is a loadh instruction. Shift the value to the left
+     by 8 bits so that disassembled code will reassemble properly.  */
+  value = ((value << 8) & 0xFF00);
+
+  (*info->fprintf_func) (info->stream, "$%04lx", value);
+}
+
+static void
+print_dollarhex_addr16l (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			 void * dis_info,
+			 long value,
+			 unsigned int attrs ATTRIBUTE_UNUSED,
+			 bfd_vma pc ATTRIBUTE_UNUSED,
+			 int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  (*info->fprintf_func) (info->stream, "$%04lx", value);
+}
+
+static void
+print_dollarhex_p (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		   void * dis_info,
+		   long value,
+		   unsigned int attrs ATTRIBUTE_UNUSED,
+		   bfd_vma pc ATTRIBUTE_UNUSED,
+		   int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  value = ((value << 14) & 0x1C000);
+  ;value = (value  & 0x1FFFF);
+  (*info->fprintf_func) (info->stream, "$%05lx", value);
+}
+
+static void
+print_dollarhex_cj (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    void * dis_info,
+		    long value,
+		    unsigned int attrs ATTRIBUTE_UNUSED,
+		    bfd_vma pc ATTRIBUTE_UNUSED,
+		    int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  value = ((value << 1) & 0x1FFFF);
+  (*info->fprintf_func) (info->stream, "$%05lx", value);
+}
+
+static void
+print_decimal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void * dis_info,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  (*info->fprintf_func) (info->stream, "%ld", value);
+}
+
+
+
+/* -- */
+

cpu/mep-c5.cpu

+; Copyright 2011 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc;
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+; Insns introduced for the MeP-c5 core
+;
+
+(dnf f-c5n4     "extended field"     (all-mep-core-isas)   16  4)
+(dnf f-c5n5     "extended field"     (all-mep-core-isas)   20  4)
+(dnf f-c5n6     "extended field"     (all-mep-core-isas)   24  4)
+(dnf f-c5n7     "extended field"     (all-mep-core-isas)   28  4)
+(dnf f-rl5      "register l c5"      (all-mep-core-isas)   20  4)
+(df  f-12s20    "extended field"     (all-mep-core-isas)   20  12  INT #f #f)
+
+(dnop rl5       "register Rl c5"     (all-mep-core-isas) h-gpr   f-rl5)
+(dnop cdisp12   "copro addend (12 bits)" (all-mep-core-isas) h-sint  f-12s20)
+
+(dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))
+     "stcb $rn,($rma)"
+     (+ MAJ_7 rn rma (f-sub4 12))
+     (c-call VOID "do_stcb" rn (and rma #xffff))
+     ((mep (unit u-use-gpr (in usereg rn))
+	   (unit u-use-gpr (in usereg rma))
+	   (unit u-exec)
+	   (unit u-stcb))))
+
+(dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))
+     "ldcb $rn,($rma)"
+     (+ MAJ_7 rn rma (f-sub4 13))
+     (set rn (c-call SI "do_ldcb" (and rma #xffff)))
+      ((mep (unit u-use-gpr (in usereg rma))
+	    (unit u-ldcb)
+	    (unit u-exec)
+	    (unit u-ldcb-gpr (out loadreg rn)))))
+
+(dnci pref "cache prefetch" ((MACH c5) VOLATILE)
+     "pref $cimm4,($rma)"
+     (+ MAJ_7 cimm4 rma (f-sub4 5))
+     (sequence ()
+	       (c-call VOID "check_option_dcache" pc)
+	       (c-call VOID "do_cache_prefetch" cimm4 rma pc))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci prefd "cache prefetch" ((MACH c5) VOLATILE)
+     "pref $cimm4,$sdisp16($rma)"
+     (+ MAJ_15 cimm4 rma (f-sub4 3) sdisp16)
+     (sequence ()
+	       (c-call VOID "check_option_dcache" pc)
+	       (c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+      "casb3 $rl5,$rn,($rm)"
+      (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0))
+      (sequence ()
+		(c-call VOID "do_casb3" (index-of rl5) rn rm pc)
+		(set rl5 rl5)
+		)
+      ((mep (unit u-use-gpr (in usereg rl5))
+	    (unit u-load-gpr (out loadreg rl5))
+	    (unit u-exec))))
+
+(dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+      "cash3 $rl5,$rn,($rm)"
+      (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x1))
+      (sequence ()
+		(c-call VOID "do_cash3" (index-of rl5) rn rm pc)
+		(set rl5 rl5)
+		)
+      ((mep (unit u-use-gpr (in usereg rl5))
+	    (unit u-load-gpr (out loadreg rl5))
+	    (unit u-exec))))
+
+(dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)
+      "casw3 $rl5,$rn,($rm)"
+      (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x2))
+      (sequence ()
+		(c-call VOID "do_casw3" (index-of rl5) rn rm pc)
+		(set rl5 rl5)
+		)
+      ((mep (unit u-use-gpr (in usereg rl5))
+	    (unit u-load-gpr (out loadreg rl5))
+	    (unit u-exec))))
+
+
+
+(dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "sbcp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 0) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+	       (set (mem QI (add rma (ext SI cdisp12))) (and crn #xff)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "lbcp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 4) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (ext SI (mem QI (add rma (ext SI cdisp12))))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "lbucp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 12) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem QI (add rma (ext SI cdisp12))))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+
+(dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "shcp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 1) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
+	       (set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "lhcp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 5) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (ext SI (mem HI (add rma (ext SI cdisp12))))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))
+     "lhucp $crn,$cdisp12($rma)"
+     (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 13) cdisp12)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem HI (add rma (ext SI cdisp12))))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+
+(dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+     "lbucpa $crn,($rma+),$cdisp10"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xC) (f-ext62 #x0) cdisp10)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem QI rma)))
+	       (set rma (add rma cdisp10)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))
+     "lhucpa $crn,($rma+),$cdisp10a2"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xD) (f-ext62 #x0) cdisp10a2)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+	       (set rma (add rma (ext SI cdisp10a2))))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lbucpm0 "lbucpm0" (OPTIONAL_CP_INSN (MACH c5))
+     "lbucpm0 $crn,($rma+),$cdisp10"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x2) cdisp10)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem QI rma)))
+	       (set rma (mod0 cdisp10)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhucpm0 "lhucpm0" (OPTIONAL_CP_INSN (MACH c5))
+     "lhucpm0 $crn,($rma+),$cdisp10a2"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x2) cdisp10a2)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+	       (set rma (mod0 cdisp10a2)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lbucpm1 "lbucpm1" (OPTIONAL_CP_INSN (MACH c5))
+     "lbucpm1 $crn,($rma+),$cdisp10"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x3) cdisp10)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem QI rma)))
+	       (set rma (mod1 cdisp10)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci lhucpm1 "lhucpm1" (OPTIONAL_CP_INSN (MACH c5))
+     "lhucpm1 $crn,($rma+),$cdisp10a2"
+     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x3) cdisp10a2)
+     (sequence ()
+	       (c-call "check_option_cp" pc)
+	       (set crn (zext SI (mem HI (and rma (inv SI 1)))))
+	       (set rma (mod1 cdisp10a2)))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))
+
+(dnci uci "uci" ((MACH c5) VOLATILE)
+     "uci $rn,$rm,$uimm16"
+     (+ MAJ_15 rn rm (f-sub4 2) simm16)
+     (set rn (c-call SI "do_UCI" rn rm (zext SI uimm16) pc))
+     ((mep (unit u-use-gpr (in usereg rm))
+	   (unit u-use-gpr (in usereg rn))
+	   (unit u-exec))))
+
+(dnf f-c5-rnm     "register n/m"              (all-mep-isas)    4  8)
+(dnf f-c5-rm      "register m"              (all-mep-isas)    8  4)
+(df  f-c5-16u16  "general 16-bit u-val"    (all-mep-isas) 16 16 UINT #f #f)
+
+(dnmf f-c5-rmuimm20 "20-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+      (f-c5-rm f-c5-16u16)
+      (sequence () ; insert
+		(set (ifield f-c5-rm)    (srl (ifield f-c5-rmuimm20) 16))
+		(set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff))
+		)
+      (sequence () ; extract
+		(set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16)
+						(sll (ifield f-c5-rm) 16)))
+		)
+      )
+(dnop c5rmuimm20 "20-bit immediate in rm and imm16" (all-mep-core-isas) h-uint f-c5-rmuimm20)
+
+(dnmf f-c5-rnmuimm24 "24-bit immediate in Rm/Imm16" (all-mep-isas) UINT
+      (f-c5-rnm f-c5-16u16)
+      (sequence () ; insert
+		(set (ifield f-c5-rnm)    (srl (ifield f-c5-rnmuimm24) 16))
+		(set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff))
+		)
+      (sequence () ; extract
+		(set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16)
+						(sll (ifield f-c5-rnm) 16)))
+		)
+      )
+(dnop c5rnmuimm24 "24-bit immediate in rn, rm, and imm16" (all-mep-core-isas) h-uint f-c5-rnmuimm24)
+
+(dnci dsp "dsp" ((MACH c5) VOLATILE)
+     "dsp $rn,$rm,$uimm16"
+     (+ MAJ_15 rn rm (f-sub4 0) uimm16)
+     (set rn (c-call SI "do_DSP" rn rm (zext SI uimm16) pc))
+     ((mep (unit u-use-gpr (in usereg rm))
+	   (unit u-use-gpr (in usereg rn))
+	   (unit u-exec))))
+
+(dnci dsp0 "dsp0" ((MACH c5) VOLATILE NO-DIS ALIAS)
+     "dsp0 $c5rnmuimm24"
+     (+ MAJ_15 c5rnmuimm24 (f-sub4 0))
+     (c-call VOID "do_DSP" (zext SI c5rnmuimm24) pc)
+     ((mep (unit u-exec))))
+
+(dnci dsp1 "dsp1" ((MACH c5) VOLATILE NO-DIS ALIAS)
+     "dsp1 $rn,$c5rmuimm20"
+     (+ MAJ_15 rn (f-sub4 0) c5rmuimm20)
+     (set rn (c-call SI "do_DSP" rn (zext SI c5rmuimm20) pc))
+     ((mep (unit u-use-gpr (in usereg rn))
+	   (unit u-exec))))

cpu/mep-default.cpu

+; Toshiba MeP Media Engine architecture description.  -*- Scheme -*-
+; Copyright 2011 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc;
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+; This file serves as a wrapper to bring in the core description plus
+; sample implementations of the UCI and DSP instructions.
+
+(include "mep-core.cpu")
+(include "mep-ext-cop.cpu")

cpu/mep-ext-cop.cpu

+; Toshiba MeP Media Engine architecture description.  -*- Scheme -*-
+; Copyright 2011 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc;
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+;; begin-user-isa-includes
+(include "mep-ivc2.cpu")
+;; end-user-isa-includes

cpu/mep-fmax.cpu

+; Toshiba MeP FMAX Coprocessor description.  -*- Scheme -*-
+; Copyright 2011 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc;
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+;------------------------------------------------------------------------------
+; MeP-Integrator will redefine the isa pmacros below to allow the bit widths
+; specified below for each ME_MODULE using this coprocessor.
+; This coprocessor requires only the 32 bit insns in the core.
+;------------------------------------------------------------------------------
+; begin-isas
+(define-pmacro fmax-core-isa () (ISA ext_core2))
+(define-pmacro all-fmax-isas () (ISA ext_core2))
+; end-isas
+
+;******************************************************************************
+; ifields
+;------------------------------------------------------------------------------
+; opcodes
+(dnf f-fmax-0-4  "opcode" (all-fmax-isas)  0 4)
+(dnf f-fmax-4-4  "opcode" (all-fmax-isas)  4 4)
+(dnf f-fmax-8-4  "opcode" (all-fmax-isas)  8 4)
+(dnf f-fmax-12-4 "opcode" (all-fmax-isas) 12 4)
+(dnf f-fmax-16-4 "opcode" (all-fmax-isas) 16 4)
+(dnf f-fmax-20-4 "opcode" (all-fmax-isas) 20 4)
+(dnf f-fmax-24-4 "opcode" (all-fmax-isas) 24 4)
+(dnf f-fmax-28-1 "opcode" (all-fmax-isas) 28 1)
+(dnf f-fmax-29-1 "opcode" (all-fmax-isas) 29 1)
+(dnf f-fmax-30-1 "opcode" (all-fmax-isas) 30 1)
+(dnf f-fmax-31-1 "opcode" (all-fmax-isas) 31 1)
+
+;------------------------------------------------------------------------------
+; FR registers
+(define-multi-ifield
+  (name f-fmax-frd)
+  (comment "FRd register")
+  (attrs all-fmax-isas)
+  (mode UINT)
+  (subfields f-fmax-28-1 f-fmax-4-4)
+  (insert (sequence ()
+		    (set (ifield f-fmax-4-4) (and (ifield f-fmax-frd) #xf))
+		    (set (ifield f-fmax-28-1) (srl (ifield f-fmax-frd) 4))))
+  (extract (set (ifield f-fmax-frd)
+		(or (sll (ifield f-fmax-28-1) 4) (ifield f-fmax-4-4))))
+)
+(define-multi-ifield
+  (name f-fmax-frn)
+  (comment "FRn register")
+  (attrs all-fmax-isas)
+  (mode UINT)
+  (subfields f-fmax-29-1 f-fmax-20-4)
+  (insert (sequence ()
+		    (set (ifield f-fmax-20-4) (and (ifield f-fmax-frn) #xf))
+		    (set (ifield f-fmax-29-1) (srl (ifield f-fmax-frn) 4))))
+  (extract (set (ifield f-fmax-frn)
+		(or (sll (ifield f-fmax-29-1) 4) (ifield f-fmax-20-4))))
+)
+(define-multi-ifield
+  (name f-fmax-frm)
+  (comment "FRm register")
+  (attrs all-fmax-isas)
+  (mode UINT)
+  (subfields f-fmax-30-1 f-fmax-24-4)
+  (insert (sequence ()
+		    (set (ifield f-fmax-24-4) (and (ifield f-fmax-frm) #xf))
+		    (set (ifield f-fmax-30-1) (srl (ifield f-fmax-frm) 4))))
+  (extract (set (ifield f-fmax-frm)
+		(or (sll (ifield f-fmax-30-1) 4) (ifield f-fmax-24-4))))
+)
+
+;------------------------------------------------------------------------------
+; Core General registers
+(dnf f-fmax-rm  "opcode" (all-fmax-isas)  8 4)
+
+;------------------------------------------------------------------------------
+; Condition opcodes enum
+(define-normal-insn-enum fmax-cond "condition opcode enum" (all-fmax-isas) FMAX_ f-fmax-8-4
+  ("f"  "u"  "e"  "ue"  "l"  "ul"  "le"  "ule"
+   "fi" "ui" "ei" "uei" "li" "uli" "lei" "ulei")
+)
+
+;******************************************************************************
+; Hardware
+;------------------------------------------------------------------------------
+; FR registers
+
+; Given a coprocessor register number N, expand to a
+; name/index pair: ($frN N)
+(define-pmacro (-fmax-fr-reg-pair n) ((.sym "fr" n) n))
+(define-pmacro (-fmax-cr-reg-pair n) ((.sym "c" n) n))
+
+; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
+; GDB will use the hardware table generated from this declaration. The operands use h-cr
+; from mep-core.cpu so that SID's semantic trace will be consistent between
+; the core and the coprocessor but use parse/print handlers which reference the hardware table
+; generated from this declarations
+(define-hardware
+  (name h-cr-fmax)
+  (comment "Floating point registers")
+  (attrs all-fmax-isas VIRTUAL IS_FLOAT)
+  (type register SF (32))
+  (indices keyword "$"
+	   (.splice (.unsplice (.map -fmax-fr-reg-pair (.iota 32)))
+		    (.unsplice (.map -fmax-cr-reg-pair (.iota 32))))
+  )
+  (get (index) (c-call SF "fmax_fr_get_handler" index))
+  (set (index newval) (c-call VOID "fmax_fr_set_handler" index newval))
+)
+
+;------------------------------------------------------------------------------
+; Control registers
+; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
+; GDB will use the hardware table generated from this declaration. The operands use h-ccr
+; from mep-core.cpu so that SID's semantic trace will be consistent between
+; the core and the coprocessor but use parse/print handlers which reference the hardware table
+; generated from this declarations
+(define-hardware
+  (name h-ccr-fmax)
+  (comment "Coprocessor Identifier and Revision Register")
+  (attrs all-fmax-isas VIRTUAL)
+  (type register USI (16))
+  (indices keyword "$" (
+		       ("cirr"  0) ("fcr0"   0) ("ccr0"   0)
+		       ("cbcr"  1) ("fcr1"   1) ("ccr1"   1)
+		       ("cerr" 15) ("fcr15" 15) ("ccr15" 15)
+                      )
+  )
+  (set (index newval) (c-call VOID "h_ccr_set" index newval))
+  (get (index) (c-call SI "h_ccr_get" index))
+)
+
+;------------------------------------------------------------------------------
+; Misc
+(define-hardware
+  (name h-fmax-compare-i-p)
+  (comment "flag")
+  (attrs all-fmax-isas)
+  (type register USI)
+)
+
+;******************************************************************************
+; Operands
+;------------------------------------------------------------------------------
+; FR Registers
+(define-full-operand fmax-FRd "FRd" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ())
+(define-full-operand fmax-FRn "FRn" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ())
+(define-full-operand fmax-FRm "FRm" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frm ((parse "fmax_cr") (print "fmax_cr")) () ())
+
+(define-full-operand fmax-FRd-int "FRd as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ())
+(define-full-operand fmax-FRn-int "FRn as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ())
+
+;------------------------------------------------------------------------------
+; Control registers
+(define-full-operand fmax-CCRn "CCRn" (all-fmax-isas (CDATA REGNUM)) h-ccr DFLT f-fmax-4-4 ((parse "fmax_ccr") (print "fmax_ccr")) () ())
+
+(dnop fmax-CIRR "CIRR" (all-fmax-isas SEM-ONLY) h-ccr 0)
+(dnop fmax-CBCR "CBCR" (all-fmax-isas SEM-ONLY) h-ccr 1)
+(dnop fmax-CERR "CERR" (all-fmax-isas SEM-ONLY) h-ccr 15)
+
+;------------------------------------------------------------------------------
+; Core General Registers
+(dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm)
+
+;------------------------------------------------------------------------------
+; misc
+(dnop fmax-Compare-i-p "flag" (all-fmax-isas SEM-ONLY) h-fmax-compare-i-p f-nil)
+
+;******************************************************************************
+; Instructions
+;------------------------------------------------------------------------------
+; Binary Arithmetic
+(define-pmacro (fmax-binary-arith op opc sem)
+  (dni op
+       (.str op " FRd,FRn,FRm")
+       (all-fmax-isas MAY_TRAP)
+       (.str op " ${fmax-FRd},${fmax-FRn},${fmax-FRm}")
+       (+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7) (f-fmax-16-4 0)
+	  fmax-FRn fmax-FRm (f-fmax-31-1 0))
+       sem
+       ()
+  )
+)
+
+(fmax-binary-arith fadds #x0 (set fmax-FRd (add fmax-FRn fmax-FRm)))
+(fmax-binary-arith fsubs #x1 (set fmax-FRd (sub fmax-FRn fmax-FRm)))
+(fmax-binary-arith fmuls #x2 (set fmax-FRd (mul fmax-FRn fmax-FRm)))
+(fmax-binary-arith fdivs #x3 (set fmax-FRd (div fmax-FRn fmax-FRm)))
+
+;------------------------------------------------------------------------------
+; Unary Arithmetic
+(define-pmacro (fmax-unary-arith op opc sem)
+  (dni op
+       (.str op " FRd,FRn")
+       (all-fmax-isas MAY_TRAP)
+       (.str op " ${fmax-FRd},${fmax-FRn}")
+       (+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7)
+	  (f-fmax-16-4 0)  fmax-FRn (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
+       sem
+       ()
+  )
+)
+
+(fmax-unary-arith fsqrts #x4 (set fmax-FRd (sqrt fmax-FRn)))
+(fmax-unary-arith fabss  #x5 (set fmax-FRd (abs fmax-FRn)))
+(fmax-unary-arith fnegs  #x7 (set fmax-FRd (neg fmax-FRn)))
+(fmax-unary-arith fmovs  #x6 (set fmax-FRd fmax-FRn))
+
+;------------------------------------------------------------------------------
+; Conversions
+(define-pmacro (fmax-conv op opc1 opc2 opnd1 opnd2 sem)
+  (dni op
+       (.str op " FRd,FRn")
+       (all-fmax-isas MAY_TRAP)
+       (.str op " ${" opnd1 "},${" opnd2 "}")
+       (+ (f-fmax-0-4 #xF) opnd1 (f-fmax-8-4 opc1) (f-fmax-12-4 #x7)
+	  (f-fmax-16-4 opc2)  opnd2 (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
+       sem
+       ()
+  )
+)
+
+(fmax-conv froundws #xC #x0 fmax-FRd-int fmax-FRn     (set fmax-FRd-int (c-call SI "fmax_froundws" fmax-FRn)))
+(fmax-conv ftruncws #xD #x0 fmax-FRd-int fmax-FRn     (set fmax-FRd-int (c-call SI "fmax_ftruncws" fmax-FRn)))
+(fmax-conv fceilws  #xE #x0 fmax-FRd-int fmax-FRn     (set fmax-FRd-int (c-call SI "fmax_fceilws" fmax-FRn)))
+(fmax-conv ffloorws #xF #x0 fmax-FRd-int fmax-FRn     (set fmax-FRd-int (c-call SI "fmax_ffloorws" fmax-FRn)))
+(fmax-conv fcvtws   #x4 #x1 fmax-FRd-int fmax-FRn     (set fmax-FRd-int (c-call SI "fmax_fcvtws" fmax-FRn)))
+(fmax-conv fcvtsw   #x0 #x9 fmax-FRd     fmax-FRn-int (set fmax-FRd (float SF FPCONV-DEFAULT fmax-FRn-int)))
+
+;------------------------------------------------------------------------------
+; Comparisons
+;
+; Comparison with no exceptions
+(define-pmacro (fmax-f-sem x y)  (andif (gt x y) (lt x y))) ; do this to get exception detection
+(define-pmacro (fmax-u-sem x y)  (not (orif (lt x y) (orif (eq x y) (gt x y)))))
+(define-pmacro (fmax-e-sem x y)  (eq x y))
+(define-pmacro (fmax-ue-sem x y) (not (orif (lt x y) (gt x y))))
+(define-pmacro (fmax-l-sem x y)  (lt x y))
+(define-pmacro (fmax-ul-sem x y) (not (orif (gt x y) (eq x y))))
+(define-pmacro (fmax-le-sem x y) (orif (lt x y) (eq x y)))
+(define-pmacro (fmax-ule-sem x y) (not (gt x y)))
+
+(define-pmacro (fmax-comp cond suffix exceptions)
+  (dni (.sym fcmp cond suffix s)
+       (.str "fcmp" cond suffix "s FRn,FRm")
+       ;; Even though the instruction doesn't really trap if EXCEPTIONS
+       ;; is zero, we don't want gcc to put it in a repeat or erepeat
+       ;; block because of the hazards between fcmp instructions and
+       ;; anything that reads CBCR.
+       (all-fmax-isas MAY_TRAP)
+       (.str "fcmp" cond suffix "s ${fmax-FRn},${fmax-FRm}")
+       (+ (f-fmax-0-4 #xF) (f-fmax-4-4 0) (.sym FMAX_ cond suffix) (f-fmax-12-4 #x7)
+	  (f-fmax-16-4 #x2) (f-fmax-28-1 0) fmax-FRn fmax-FRm (f-fmax-31-1 0))
+       (sequence ()
+		 (set fmax-Compare-i-p exceptions)
+		 (set fmax-CBCR ((.sym fmax- cond -sem) fmax-FRn fmax-FRm))
+		 (set fmax-Compare-i-p 0)
+       )
+       ()
+  )
+)
+
+; Comparison with no exceptions
+(fmax-comp f   "" 0)
+(fmax-comp u   "" 0)
+(fmax-comp e   "" 0)
+(fmax-comp ue  "" 0)
+(fmax-comp l   "" 0)
+(fmax-comp ul  "" 0)
+(fmax-comp le  "" 0)
+(fmax-comp ule "" 0)
+
+; Comparison with exceptions
+(fmax-comp f   i 1)
+(fmax-comp u   i 1)
+(fmax-comp e   i 1)
+(fmax-comp ue  i 1)
+(fmax-comp l   i 1)
+(fmax-comp ul  i 1)
+(fmax-comp le  i 1)
+(fmax-comp ule i 1)
+
+;------------------------------------------------------------------------------
+; Move to/from core registers
+(dni cmov-frn-rm
+     "cmov FRn,Rm"
+     (all-fmax-isas (INTRINSIC "cmov1"))
+     "cmov ${fmax-FRd-int},${fmax-Rm}"
+     (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
+	(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
+	(f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
+     (set fmax-FRd-int fmax-Rm)
+     ()
+)
+(dni cmov-rm-frn
+     "cmov Rm,FRn"
+     (all-fmax-isas (INTRINSIC "cmov2"))
+     "cmov ${fmax-Rm},${fmax-FRd-int}"
+     (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
+	(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
+	(f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 1))
+     (set fmax-Rm fmax-FRd-int)
+     ()
+)
+(dni cmovc-ccrn-rm
+     "cmovc CCRn,Rm"
+     (all-fmax-isas (INTRINSIC "cmovc1"))
+     "cmovc ${fmax-CCRn},${fmax-Rm}"
+     (+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7)
+	(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
+	(f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 0))
+     (set fmax-CCRn fmax-Rm)
+     ()
+)
+(dni cmovc-rm-ccrn
+     "cmovc Rm,CCRn"
+     (all-fmax-isas (INTRINSIC "cmovc2"))
+     "cmovc ${fmax-Rm},${fmax-CCRn}"
+     (+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7)
+	(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
+	(f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 1))
+     (set fmax-Rm fmax-CCRn)
+     ()
+)

cpu/mep-h1.cpu

+; Copyright 2011 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc;
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+; Insns introduced for the MeP-h1 core
+;
+(dnci stcb_r "store in control bus space" (VOLATILE (MACH h1))
+     "stcb $rn,($rma)"
+     (+ MAJ_7 rn rma (f-sub4 12))
+     (c-call VOID "do_stcb" rn (and rma #xffff))
+     ((mep (unit u-use-gpr (in usereg rn))
+	   (unit u-use-gpr (in usereg rma))
+	   (unit u-exec)
+	   (unit u-stcb))))
+
+(dnci ldcb_r "load from control bus space" (VOLATILE (MACH h1) (LATENCY 3))
+     "ldcb $rn,($rma)"
+     (+ MAJ_7 rn rma (f-sub4 13))
+     (set rn (c-call SI "do_ldcb" (and rma #xffff)))
+      ((mep (unit u-use-gpr (in usereg rma))
+	    (unit u-ldcb)
+	    (unit u-exec)
+	    (unit u-ldcb-gpr (out loadreg rn)))))
+
+(dnci pref "cache prefetch" ((MACH h1) VOLATILE)
+     "pref $cimm4,($rma)"
+     (+ MAJ_7 cimm4 rma (f-sub4 5))
+     (sequence ()
+	       (c-call VOID "check_option_dcache" pc)
+	       (c-call VOID "do_cache_prefetch" cimm4 rma pc))
+     ((mep (unit u-use-gpr (in usereg rma))
+	   (unit u-exec))))

cpu/mep.cpu

+; Copyright 2011 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc;
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+(include "mep-default.cpu")