cris.cpu

; CRIS CPU description.  -*- Scheme -*-
;
; Copyright 2003, 2004, 2007 Free Software Foundation, Inc.
;
; Contributed by Axis Communications AB.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
; MA 02110-1301, USA.

(include "simplify.inc")

;;;;;;;;;;;;;;;;;; -pmacro (generic ones)

(define-pmacro (.car2 l) (.apply (.pmacro (a b) a) l))
(define-pmacro (.cadr2 l) (.apply (.pmacro (a b) b) l))
(define-pmacro (SI-ext x) "How to sign-extend a dword to dword (a nop)" x)
(define-pmacro (HI-ext x) "How to sign-extend a word to dword" (ext SI x))
(define-pmacro (QI-ext x) "How to sign-extend a byte to dword" (ext SI x))
(define-pmacro (SI-zext x) "How to zero-extend a dword to dword (a nop)" x)
(define-pmacro (HI-zext x) "How to zero-extend a word to dword" (zext SI x))
(define-pmacro (QI-zext x) "How to zero-extend a byte to dword" (zext SI x))
(define-pmacro
  (define-pmacro-map x)
  "On a list ((x0 y0) .. (xN yN)), 0 <= m <= N, (define-pmacro xm ym)"
  (.splice
   begin
   (.unsplice
    (.map
     (.pmacro (l) (.apply (.pmacro (xm ym) (define-pmacro xm ym)) l)) x)))
)

;;;;;;;;;;;;;;;;;; -arch -isa -cpu -model

(define-arch
  (name cris)
  (comment "Axis Communications CRIS")
  (default-alignment unaligned)
  (insn-lsb0? #t)
  (machs crisv0 crisv3 crisv8 crisv10 crisv32)
  (isas cris)
)

(define-isa
  (name cris)
  (base-insn-bitsize 16)
  (liw-insns 1)
  (parallel-insns 1)
)

(define-pmacro
  (define-cpu-cris x-suffix x-comment)
  "Define a CRIS CPU family"
  (define-cpu
    (name (.sym cris x-suffix f))
    (comment x-comment)
    (endian little)
    ; CGEN-FIXME: Should be deduced from the default?
    (word-bitsize 32)
    (file-transform (.str x-suffix))
  )
)

; Useful when there's a need to iterate over all models.
(define-pmacro (cris-cpu-model-numbers)
  "List of CRIS CPU model numbers (version register contents)"
  (0 3 8 10 32)
)

(define-pmacro (cris-cpu-models)
  "List of CRIS CPU model names"
  (.map (.pmacro (n) (.sym v n)) (cris-cpu-model-numbers))
)

; Mapping from model name to number.
(define-pmacro-map
  (.map (.pmacro (n) ((.sym v n -number) n))
	(cris-cpu-model-numbers)))

; FIXME: Rationalize these rules.
; CPU names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
; We ignore the "b" convention, partly because v0 isn't really a "base", at
; least not for some aspects of v32.
(define-cpu-cris v0 "CRIS base family")
(define-cpu-cris v3 "CRIS v3 family")
(define-cpu-cris v8 "CRIS v8 family")
(define-cpu-cris v10 "CRIS v10 family")
(define-cpu-cris v32 "CRIS v32 family")

(define-pmacro MACH-PRE-V32 (MACH crisv0,crisv3,crisv8,crisv10))
(define-pmacro MACH-V3-UP (MACH crisv3,crisv8,crisv10,crisv32))
(define-pmacro MACH-V32 (MACH crisv32))
(define-pmacro MACH-PC MACH-PRE-V32)
(define-pmacro MACH-ACR MACH-V32)
(define-pmacro MACH-BRANCH-OFFSET-AT-INSN MACH-V32)
(define-pmacro MACH-BRANCH-OFFSET-AFTER-INSN MACH-PRE-V32)

(define-pmacro
  current-mach-is-v32
  "Whether the generated code is for V32.  See comment at h-v32."
  (reg h-v32)
)

(define-pmacro (define-mach-cris x-suffix x-comment x-name)
  "Define a CRIS mach"
  (define-mach
    (name (.sym cris x-suffix))
    ; They're all called "cris" in bfd.  Watch out for breakages for some
    ; uses.
    (bfd-name x-name)
    (comment x-comment)
    (cpu (.sym cris x-suffix f)))
)

(define-mach-cris v0 "Generic CRIS v0 CPU, ETRAX 1 .. 3" "cris")
(define-mach-cris v3 "Generic CRIS v3 CPU, ETRAX 4" "cris")
(define-mach-cris v8 "Generic CRIS v8 CPU, ETRAX 100" "cris")
(define-mach-cris v10 "Generic CRIS v10 CPU, ETRAX 100 LX" "cris")
(define-mach-cris v32 "Generic CRIS v32 CPU, ETRAX FS" "crisv32")

(define-pmacro (define-model-simplecris x-name x-comment)
  "Define a simple CRIS model"
  (define-model
    (name (.sym cris x-name))
    (comment x-comment)
    (mach (.sym cris x-name))

    (unit u-exec "Execution Unit" () 1 1 () () () ())
    (unit u-mem "Memory Unit" () 1 1 () () () ())

    (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ())
    (unit u-const32 "Fetch 32-bit operand" () 1 1
	  () () () ())
    ; Used in special-case insn, for example arithmetic with PC destination.
    (unit u-stall "Stall unit" () 1 1 () () () ())
    (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ())
    (unit u-multiply "Multiply Unit" () 1 1 ((MACH crisv10)) () () ())
    (unit u-movem "Movem Unit" () 1 1 ()
	  ((Rd INT -1))
	  () ()))
)

(define-model-simplecris v0 "Model of CRIS v0, ETRAX 1 .. 3")
(define-model-simplecris v3 "Model of CRIS v3, ETRAX 4")
(define-model-simplecris v8 "Model of CRIS v8, ETRAX 100")
(define-model-simplecris v10 "Model of CRIS v10, ETRAX 100 LX")

; For some reason, we get an error:
;  Generating arch.h ...
;  ERROR: In procedure vector-ref:
;  ERROR: Wrong type argument in position 1: ()
; if we include timings for machs that we don't generate sims for.
; Last checked: CVS as of 2004-11-18.
; CGEN-FIXME: Looks like another CGEN bug.  When it's fixed (or when
; generating sims for v0, v3 or v8), add 0, 3 and 8 to
; simplecris-timing-models.  But before that, simplecris-timing-x has to
; be rewritten to work on a multiple-element-list, not assume a single
; element.  (A change which seems likely to depend on lexical scoping for
; macros to be introduced: try the obvious implementation.)
(define-pmacro simplecris-timing-models (10))
(define-pmacro (simplecris-common-timing x-units)
  "Make timing models, using x-units for all simplecris-timing-models"
  ; CGEN-FIXME: Another CGEN bug: the part (.unsplice (10)) will remain
  ; unexpanded in (.sym crisv (.unsplice (10)) if we write this as
  ; ((.splice (.sym crisv (.unsplice simplecris-timing-models))
  ;	      (.unsplice x-units)))
  ((.splice (.sym crisv (.apply (.pmacro (x) x) simplecris-timing-models))
  	    (.unsplice x-units)))
)

(define-pmacro-map
  (
   ; Timing for memory instructions running on a simple cris model.
   ((simplecris-mem-timing)	(simplecris-common-timing
				 ((unit u-mem) (unit u-exec))))
   ; Timing for movem instructions running on a simple cris model.
   ((simplecris-movem-timing)	(simplecris-common-timing
				 ((unit u-movem) (unit u-exec))))
   ; Similar, for an 8- or 16-bit constant ([PC+]) operand.
   ((simplecris-const-timing-HI)
				(simplecris-common-timing
				 ((unit u-const16) (unit u-exec))))
   ; Similar, for a 32-bit constant ([PC+]) operand.
   ((simplecris-const-timing-SI)
				(simplecris-common-timing
				 ((unit u-const32) (unit u-exec))))
   ; Similar, no particular operand.
   ((simplecris-timing)		(simplecris-common-timing
				 ((unit u-exec)))))
)

(define-model
  (name crisv32)
  (comment "Model of CRISv32")
  (mach crisv32)

  (state
    ; Bitmask of h-gr register (0..15) and h-sr register (17..31)
    ; modified by 3rd previous insn, updated by the u-exec unit.
    ; Because there's no need to mark writes to special registers BZ and
    ; WZ, bit 16 is for jump mark and bit 20 for memory-write mark.
    (prev-prev-prev-modf-regs UINT)

    ; Ditto for the 2nd previous insn.
    (prev-prev-modf-regs UINT)

    ; Ditto for the previous insn.
    (prev-modf-regs UINT)

    ; Bit-mask for regs modified by the current insn, propagated to
    ; prev-modf-regs.
    (modf-regs UINT)

    ; Registers loaded by movem are not forwarded to the execution
    ; stage, so we need to insert stall-cycles for ordinary insns
    ; accessing such registers.  In addition to the *modf-regs
    ; above, these are set to tell *ordinary* insns which registers
    ; are inaccessible.

    (prev-prev-prev-movem-dest-regs UINT)

    ; Ditto for the 2nd previous insn.
    (prev-prev-movem-dest-regs UINT)

    ; Ditto for the previous insn.
    (prev-movem-dest-regs UINT)

    ; Bit-mask for regs modified by the current insn, propagated to
    ; prev-movem-dest-regs.
    (movem-dest-regs UINT))

  ; It seems this pipeline description isn't used at all; this is just
  ; for show.
  ; Noteworthy is the placement of the memory stage before the execute stage.
  (pipeline all "" () ((fetch) (decode) (memory) (execute) (writeback)))

  ; Units that contribute only a constant pipeline delay are not included.
  (unit u-mem "Memory Unit" () 1 1 ()
	((Rs INT -1))
	() ())

  ; Artificial units for read/write-related hazard accounting.
  (unit u-mem-r "Memory Unit Read" () 1 1 () () () ())
  (unit u-mem-w "Memory Unit Write" () 1 1 () () () ())

  (unit u-movem-rtom "Movem-to-memory Unit" () 1 1 ()
	((Rs INT -1) (Rd INT -1))
	() ())
  (unit u-movem-mtor "Movem-to-register Unit" () 1 1 ()
	((Rs INT -1) (Rd INT -1))
	() ())
  (unit u-multiply "Multiply Unit" () 1 1 ()
	((Rs INT -1) (Rd INT -1))
	() ())
  (unit u-branch "Branch Unit" () 1 1 ()
	()
	() ())
  (unit u-jump-r "Jump-to-register Unit" () 1 1 ()
	((Rs INT -1))
	() ())
  (unit u-jump-sr "Jump-to-special-register Unit" () 1 1 ()
	((Ps INT -1))
	() ())
  (unit u-jump "JAS/BAS Unit, saving PC" () 1 1 ()
	()
	((Pd INT -1)) ())

  ; To keep track of PC; not really functional units.
  (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ())
  (unit u-const32 "Fetch 32-bit operand" () 1 1 () () () ())
  (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ())

  ; For v32, we need to keep track of inputs (for movem destination
  ; cycle penalties) and output (for e.g. memory source and jump
  ; source cycle penalties).
  (unit u-exec "Execution Unit" () 1 1 ()
	((Rd INT -1) (Rs INT -1))
	((Rd INT -1))
	())

  ; Special case of u-exec for movem: don't treat Rd as an incoming
  ; parameter.
  (unit u-exec-movem "Execution Unit" () 1 1 ()
	((Rs INT -1))
	((Rd INT -1))
	())

  ; Special case of u-exec when the destination is a special
  ; register.
  (unit u-exec-to-sr "Execution Unit" () 1 1 ()
	((Rs INT -1))
	((Pd INT -1)) ())
)

(define-pmacro (crisv32-timing-destreg d)
  "Timing for instructions running on a crisv32 model"
  ((crisv32
    (.splice unit u-exec (.unsplice d))))
)
(define-pmacro (crisv32-timing) (crisv32-timing-destreg ()))

(define-pmacro (cris-timing-Rd-sfield)
  (crisv32-timing-destreg ((out Rd Rd-sfield)))
)

(define-pmacro (crisv32-timing-c-HI)
  ((crisv32 (unit u-const16) (unit u-exec)))
)

(define-pmacro-map
  ((crisv32-timing-c-QI crisv32-timing-c-HI)
   ((crisv32-timing-c-SI) ((crisv32 (unit u-const32) (unit u-exec))))
   ((crisv32-timing-c-sr-SI) ((crisv32 (unit u-const32) (unit u-exec-to-sr))))
   ((crisv32-reg-sr-timing) ((crisv32 (unit u-exec-to-sr))))
   ((crisv32-mem-sr-timing)
    ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec-to-sr))))
   ((crisv32-mem-timing) ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec))))
   ((crisv32-mem-write-timing) ((crisv32 (unit u-mem) (unit u-exec) (unit u-mem-w)))))
)

(define-pmacro-map
  (
   ; Timing for instructions using memory operands.
   ((cris-mem-timing)		(.splice (.unsplice (simplecris-mem-timing))
					 (.unsplice (crisv32-mem-timing))))
  ; Timing for instructions using memory operands.
   ((cris-mem-write-timing)	(.splice
				 (.unsplice (simplecris-mem-timing))
				 (.unsplice (crisv32-mem-write-timing))))
   ; Timing for moves from general register to special register.
   ((cris-reg-sr-timing)	(.splice (.unsplice (simplecris-timing))
					 (.unsplice (crisv32-reg-sr-timing))))
   ; Timing for moves from memory to special register.
   ((cris-mem-sr-timing)	(.splice (.unsplice (simplecris-mem-timing))
					 (.unsplice (crisv32-mem-sr-timing))))
   ; Timing for non-mul, non-memory, non-special-register, 16-bit instructions.
   ((cris-timing)		(.splice (.unsplice (simplecris-timing))
					 (.unsplice (crisv32-timing))))
   ; Timing for instructions with 8- or 16-bit constant operand ([PC+]).
   ((cris-timing-const-HI)	(.splice
				 (.unsplice (simplecris-const-timing-HI))
				 (.unsplice (crisv32-timing-c-HI))))
   ; Timing for instructions with a 32-bit constant operand ([PC+]).
   ((cris-timing-const-SI)	(.splice
				 (.unsplice (simplecris-const-timing-SI))
				 (.unsplice (crisv32-timing-c-SI))))
   ; Like cris-timing-const-SI, but destination special register.
   ((cris-timing-const-sr-SI)	(.splice
				 (.unsplice (simplecris-const-timing-SI))
				 (.unsplice (crisv32-timing-c-sr-SI))))
   ; Like cris-timing-const-HI, but destination special register.
   ((cris-timing-const-sr-HI)	(.splice
				 (.unsplice (simplecris-const-timing-HI))
				 (.unsplice (crisv32-timing-c-sr-SI)))))
)

(define-pmacro cris-timing-const-QI cris-timing-const-HI)
(define-pmacro cris-timing-const-sr-QI cris-timing-const-sr-HI)

(define-pmacro (simplecris-common-writable-specregs)
  "The common writable special registers in pre-v32 models."
  ((HI 5) (SI 9) (SI 10) (SI 11) (SI 12) (SI 13))
)

(define-pmacro (simplecris-common-readable-specregs)
  "The common readable special registers in pre-v32 models."
  (.splice (.unsplice (simplecris-common-writable-specregs))
	   (QI 0) (QI 1) (HI 4) (SI 8))
)

(define-pmacro (cris-implemented-writable-specregs-v0)
  "Special writable registers in v0 and their sizes"
  (.splice (.unsplice (simplecris-common-writable-specregs)) (HI 6) (HI 7))
)
(define-pmacro
  cris-implemented-specregs-const-v0
  cris-implemented-writable-specregs-v0
)
(define-pmacro (cris-implemented-readable-specregs-v0)
  "Special readable registers in v0 and their sizes"
  (.splice (.unsplice (simplecris-common-readable-specregs)) (HI 6) (HI 7))
)

(define-pmacro (cris-implemented-writable-specregs-v3)
  "Special writable registers in v3 and their sizes"
  (.splice (.unsplice (cris-implemented-writable-specregs-v0)) (SI 14))
)
(define-pmacro
  cris-implemented-specregs-const-v3
  cris-implemented-writable-specregs-v3
)
(define-pmacro (cris-implemented-readable-specregs-v3)
  "Special readable registers in v3 and their sizes"
  (.splice (.unsplice (cris-implemented-readable-specregs-v0)) (SI 14))
)

(define-pmacro (cris-implemented-writable-specregs-v8)
  "Special writable registers in v8 and their sizes"
  (.splice (.unsplice (simplecris-common-writable-specregs)) (SI 14))
)
(define-pmacro
  cris-implemented-specregs-const-v8
  cris-implemented-writable-specregs-v8
)
(define-pmacro (cris-implemented-readable-specregs-v8)
  "Special readable registers in v8 and their sizes"
  (.splice (.unsplice (simplecris-common-readable-specregs)) (SI 14))
)

(define-pmacro (cris-implemented-writable-specregs-v10)
  "Special writable registers in v10 and their sizes"
  (.splice (.unsplice (simplecris-common-writable-specregs))
	   (SI 7) (SI 14) (SI 15))
)
(define-pmacro
  cris-implemented-specregs-const-v10
  cris-implemented-writable-specregs-v10
)
(define-pmacro (cris-implemented-readable-specregs-v10)
  "Special registers in v10 and their sizes"
  (.splice (.unsplice (simplecris-common-readable-specregs))
	   (SI 7) (SI 14) (SI 15))
)

(define-pmacro (cris-implemented-writable-specregs-v32)
  "Special writable registers in v32 and their sizes"
  ((QI 2) (QI 3)
   (SI 5) (SI 6) (SI 7) (SI 9)
   (SI 10) (SI 11) (SI 12) (SI 13) (SI 14) (SI 15))
)
(define-pmacro (cris-implemented-readable-specregs-v32)
  "Special readable registers in v32 and their sizes"
  (.splice (.unsplice (cris-implemented-writable-specregs-v32))
	   (QI 0) (QI 1) (HI 4) (SI 8))
)

; For v32, all special register operations on constants (that is,
; move) take 32-bit operands, not the real size of the register, as in
; other move operations.
(define-pmacro (cris-implemented-specregs-const-v32)
  (.map (.pmacro (x) (SI (.cadr2 x)))
	(cris-implemented-writable-specregs-v32))
)

(define-pmacro cris-swap-codes
  "CRIS Swap codes in numeric order (no zero)"
  (   r  b  br  w  wr  wb  wbr
   n nr nb nbr nw nwr nwb nwbr)
)

(define-pmacro cris-flagnames
  "CRIS flag field values, dest and src fields concatenated"
  (c v z n x i u p) ; ... b m for pre-v32
)

(define-pmacro-map
  ; Bitnumber for each respective flag.
  (.map (.pmacro (x num) ((.sym x -bitnumber) num))
	cris-flagnames (.iota 8))
)

; I give up.  Here's a perl-script to get the values I want for this macro
; (not working along list principles, though).  You can run this region.
; perl -e '$x = "cvznxiup"; for ($i = 0; $i < 256; $i++) { $s = "";
;  for ($j = 0; $j < 8; $j++) { if ($i & (1 << $j)) {
; $s .= substr ($x, $j, 1);}}
; printf ("%s%s", $s eq "" ? "_" : $s, (($i + 1) % 8) == 0 ? "\n   " : " "); }'
(define-pmacro cris-flag-combinations
  "Combinations of flags in numeric order"
  (_ c v cv z cz vz cvz
   n cn vn cvn zn czn vzn cvzn
   x cx vx cvx zx czx vzx cvzx
   nx cnx vnx cvnx znx cznx vznx cvznx
   i ci vi cvi zi czi vzi cvzi
   ni cni vni cvni zni czni vzni cvzni
   xi cxi vxi cvxi zxi czxi vzxi cvzxi
   nxi cnxi vnxi cvnxi znxi cznxi vznxi cvznxi
   u cu vu cvu zu czu vzu cvzu
   nu cnu vnu cvnu znu cznu vznu cvznu
   xu cxu vxu cvxu zxu czxu vzxu cvzxu
   nxu cnxu vnxu cvnxu znxu cznxu vznxu cvznxu
   iu ciu viu cviu ziu cziu vziu cvziu
   niu cniu vniu cvniu zniu czniu vzniu cvzniu
   xiu cxiu vxiu cvxiu zxiu czxiu vzxiu cvzxiu
   nxiu cnxiu vnxiu cvnxiu znxiu cznxiu vznxiu cvznxiu
   p cp vp cvp zp czp vzp cvzp
   np cnp vnp cvnp znp cznp vznp cvznp
   xp cxp vxp cvxp zxp czxp vzxp cvzxp
   nxp cnxp vnxp cvnxp znxp cznxp vznxp cvznxp
   ip cip vip cvip zip czip vzip cvzip
   nip cnip vnip cvnip znip cznip vznip cvznip
   xip cxip vxip cvxip zxip czxip vzxip cvzxip
   nxip cnxip vnxip cvnxip znxip cznxip vznxip cvznxip
   up cup vup cvup zup czup vzup cvzup
   nup cnup vnup cvnup znup cznup vznup cvznup
   xup cxup vxup cvxup zxup czxup vzxup cvzxup
   nxup cnxup vnxup cvnxup znxup cznxup vznxup cvznxup
   iup ciup viup cviup ziup cziup vziup cvziup
   niup cniup vniup cvniup zniup czniup vzniup cvzniup
   xiup cxiup vxiup cvxiup zxiup czxiup vzxiup cvzxiup
   nxiup cnxiup vnxiup cvnxiup znxiup cznxiup vznxiup cvznxiup
  )
)

(define-pmacro cc-condition (not cbit))
(define-pmacro cs-condition cbit)
(define-pmacro ne-condition (not zbit))
(define-pmacro eq-condition zbit)
(define-pmacro vc-condition (not vbit))
(define-pmacro vs-condition vbit)
(define-pmacro pl-condition (not nbit))
(define-pmacro mi-condition nbit)
(define-pmacro ls-condition (or cbit zbit))
(define-pmacro hi-condition (not (or cbit zbit)))
(define-pmacro ge-condition (not (xor vbit nbit)))
(define-pmacro lt-condition (xor vbit nbit))
(define-pmacro gt-condition (not (or (xor vbit nbit) zbit)))
(define-pmacro le-condition (or (xor vbit nbit) zbit))
(define-pmacro a-condition 1)

; FIXME: define this properly for v10 and pre-v10.
(define-pmacro wf-condition pbit)

(define-pmacro (cris-condition condno)
  "Return condition state for condition number CONDNO"
  (sequence
    BI
    ((SI tmpcond) (BI condres))
    (set tmpcond condno)
     (.splice
      cond
      (.unsplice
       (.map
	(.pmacro
	 (condn condc)
	 ((eq tmpcond condn) (set condres (.sym condc -condition))))
	(.iota 16)
	cris-condition-codes)))
     condres)
)

;;;;;;;;;;;;;;;;;; -keyword

; General registers.
(define-pmacro (cris-general-gregs)
  (.splice (SP 14) (.unsplice (.map (.pmacro (n) ((.sym R n) n)) (.iota 15))))
)

; Can't keep more than one gr-names definition at the same time;
; generated enum declarations in sim/cris/cris-desc.h will collide.
; FIXME: (include "different-mach-parts")

(define-keyword
  (name gr-names-pcreg)
  (attrs MACH-PC)
  (print-name h-gr-real-pc)
  ; Put PC first so it is preferred over r15.
  (.splice values (PC 15) (.unsplice (cris-general-gregs)))
)

(define-keyword
  (name gr-names-acr)
  (attrs MACH-ACR)
  ; The print-name directive will control the enum prefix.  With the
  ; arguably more appropriate h-gr-v32 or h-gr-acr, we'd get names like
  ; H_GR_ACR_R0 instead of H_GR_R0.  Since we have to choose something for
  ; unprefixed names, we use the CRISv32 names.  FIXME: All users should
  ; change to use H_GR_V32_R0 (etc.), then change this to h-gr-v32.
  (print-name h-gr)
  ; Put ACR first so it is preferred over r15.
  (.splice values (ACR 15) (.unsplice (cris-general-gregs)))
)

(define-keyword
  (name gr-names-v32)
  (attrs MACH-V32)
  ; In preparation for implementing the FIXME above.
  (print-name h-gr-v32)
  ; Put ACR first so it is preferred over r15.
  (.splice values (ACR 15) (.unsplice (cris-general-gregs)))
)

; Special registers with names common to all.
(define-pmacro (cris-general-pregs)
  (.splice
   (VR 1)
   (SRP 11)
   (.unsplice (.map (.pmacro (n) ((.sym P n) n)) (.iota 15))))
)

(define-keyword
  (name p-names-v10)
  (attrs MACH-PRE-V32)
  (print-name h-sr-pre-v32)
  (.splice
   values
   (CCR 5)
   (MOF 7)
   (IBR 9)
   (IRP 10)
   (BAR 12)
   (DCCR 13)
   (BRP 14)
   (USP 15)
   (.unsplice (cris-general-pregs)))
)

(define-keyword
  (name p-names-v32)
  (attrs MACH-V32)
  ; See comment for gr-names-acr.
  (print-name h-sr)
  (.splice
   values
   (BZ 0)
   (PID 2)
   (SRS 3)
   (WZ 4)
   (EXS 5)
   (EDA 6)
   (MOF 7)
   (DZ 8)
   (EBP 9)
   (ERP 10)
   (NRP 12)
   (CCS 13)
   (USP 14)
   (SPC 15)
   (.unsplice (cris-general-pregs)))
)

; Similarly as for h-gr-v32, in preparation.
(define-keyword
  (name p-names-v32-x)
  (attrs MACH-V32)
  ; See comment for gr-names-acr.
  (print-name h-sr-v32)
  (.splice
   values
   (BZ 0)
   (PID 2)
   (SRS 3)
   (WZ 4)
   (EXS 5)
   (EDA 6)
   (MOF 7)
   (DZ 8)
   (EBP 9)
   (ERP 10)
   (NRP 12)
   (CCS 13)
   (USP 14)
   (SPC 15)
   (.unsplice (cris-general-pregs)))
)

(define-pmacro p0 (reg h-sr 0))
(define-pmacro vr (reg h-sr 1))
(define-pmacro pid (reg h-sr 2))
(define-pmacro srs (reg h-sr 3))
(define-pmacro p4 (reg h-sr 4))
(define-pmacro ccr (reg h-sr 5))
(define-pmacro mof (reg h-sr 7))
(define-pmacro p8 (reg h-sr 8))
(define-pmacro ibr (reg h-sr 9))
(define-pmacro ebp (reg h-sr 9))
(define-pmacro erp (reg h-sr 10))
(define-pmacro srp (reg h-sr 11))
(define-pmacro ccs (reg h-sr 13))
(define-pmacro dccr (reg h-sr 13))
(define-pmacro usp (reg h-sr 14))
(define-pmacro spc (reg h-sr 15))

(define-pmacro sp (reg h-gr 14))
(define-pmacro acr (reg h-gr 15))

(define-pmacro cris-condition-codes
  "CRIS condition codes in numeric order"
  (cc cs ne eq vc vs pl mi ls hi ge lt gt le a wf)
)

; No use having different lists; this is the only CC that
; differs between v10 and v32, and mostly in the name.
(define-pmacro sb wf)


;;;;;;;;;;;;;;;;;; -hardware

;; Various constant generators.

(define-hardware
  (name h-inc)
  (comment "autoincrement-bit syntax specifier")
  (type immediate (UINT 1))
  (values keyword "" (("" 0) ("+" 1)))
)

(define-hardware
  (name h-ccode)
  (comment "Condition code specifier")
  (type immediate (UINT 4))
  (values keyword ""
	  (.map (.pmacro (x y) ((.str x) y))
		cris-condition-codes (.iota 16)))
)

(define-hardware
  (name h-swap)
  (comment "Swap option specifier")
  (type immediate (UINT 4))
  (values
   keyword ""
   (.splice
    (" " 0)
    (.unsplice
     (.map
      (.pmacro (x y) ((.str x) y)) cris-swap-codes (.iota 15 1)))))
)

(define-hardware
  (name h-flagbits)
  (comment "Flag bits specifier")
  (type immediate (UINT 8))
  (values
   keyword ""
   (.map (.pmacro (x y) ((.str x) y)) cris-flag-combinations (.iota 256)))
)

; Apparently, the semantic-name isn't used for accessors, so external
; users like the sim glue and SID sees the -v32 and -pre-v32 munged names.
; Defining "dispatchers"; virtual registers whose getter and setter works
; on the "real" mach variants, seems to help.  CGEN-FIXME: Make
; semantic-name set the generated names.
(define-pmacro (cris-d-hwreg x-name x-type)
  (define-hardware
    (name x-name)
    (comment (.str "Dispatcher for " x-name))
    (attrs VIRTUAL)
    (type register x-type)
    (get () (reg (.sym x-name -x)))
    (set (val) (set (reg (.sym x-name -x)) val)))
)
(define-pmacro (cris-d-hwregf-a x-name x-type x-n x-attrs)
  (define-hardware
    (name x-name)
    (comment (.str "Dispatcher for " x-name))
    (.splice attrs VIRTUAL (.unsplice x-attrs))
    (type register x-type (x-n))
    (get (index) (reg (.sym x-name -x) index))
    (set (index val) (set-quiet (reg (.sym x-name -x) index) val)))
)
(define-pmacro (cris-d-hwregf x-name x-type x-n)
  (cris-d-hwregf-a x-name x-type x-n ())
)
(define-pmacro (cris-d-hwregf-p x-name x-type x-n)
  (cris-d-hwregf-a x-name x-type x-n (PROFILE))
)

; At first glance we could use (eq-attr (current-mach) ...) for
; everything, but that seems sometimes (always?) to yield false.  For
; ifields, it causes noncompilable C-code.  For the insn semantics code,
; it causes tests movei.ms and mulv32.ms to fail, apparently because the
; current-mach-is-v32 usage in flags setting is miscompiled as 0 (or
; rather, misgenerated).  Instead we use different definitions of a
; MACH-tagged virtual register yielding a constant, together with a
; pmacro.  CGEN-FIXME: If eq-attr is someday fixed, we could just remove
; these h-v32 virtual register definitions and change the pmacro
; definition for current-mach-is-v32.
(define-hardware
  (semantic-name h-v32)
  (name h-v32-v32)
  (attrs MACH-V32 VIRTUAL)
  (type register BI)
  (get () (const BI 1))
  (set (val) (error "Can't set h-v32"))
)
(define-hardware
  (semantic-name h-v32)
  (name h-v32-non-v32)
  (attrs MACH-PRE-V32 VIRTUAL)
  (type register BI)
  (get () (const BI 0))
  (set (val) (error "Can't set h-v32"))
)

;; "Real" hardware.

(define-hardware
  (name h-pc)
  (comment "program counter")
  (attrs PC PROFILE)
  (type pc)
  ; There's no bit 0 in PC, so just ignore it when jumping etc.
  (set (val) (set (raw-reg h-pc) (and val (inv 1))))
)

; Note that setting register 15 isn't handled here, but in each insn, so
; the proper "jump" attributes and other special stuff for speedy
; execution can be present.
(cris-d-hwregf-p h-gr SI 16)
(define-hardware
  (semantic-name h-gr-x)
  (name h-gr-pc)
  (attrs MACH-PC VIRTUAL)
  (comment "General purpose registers, aborting on PC access")
  (type register SI (16))
  (indices extern-keyword gr-names-pcreg)
  (get
   (index)
   (if SI (eq index 15)
       (error SI "General register read of PC is not implemented.")
       (reg SI h-gr-real-pc index)))
  (set
   (index val)
   (sequence
     ()
     (if (eq index 15)
	 (error "General register write to PC is not implemented."))
     (set (reg SI h-gr-real-pc index) val)))
)
(define-hardware
  (name h-gr-real-pc)
  (attrs MACH-PC)
  (comment "General purpose registers")
  (type register SI (16))
  (indices extern-keyword gr-names-pcreg)
)

; We have to use a virtual register trick to get the "raw", unaccounted
; contents of the global register; the raw-reg RTX only works for
; non-virtual register files.
(define-hardware
  (semantic-name h-raw-gr)
  (name h-raw-gr-pc)
  (attrs MACH-PC VIRTUAL)
  (comment "Unaccounted version of general purpose registers")
  (type register SI (16))
  (get (index) (raw-reg h-gr-real-pc index))
  (set (index val) (set-quiet (raw-reg h-gr-real-pc index) val))
)
(define-hardware
  (semantic-name h-gr-x)
  (name h-gr-acr)
  (attrs MACH-ACR)
  (comment "General purpose registers")
  (type register SI (16))
  (indices extern-keyword gr-names-acr)
)
(define-hardware
  (semantic-name h-raw-gr)
  (name h-raw-gr-acr)
  (attrs MACH-ACR VIRTUAL)
  (comment "Unaccounted version of general purpose registers")
  (type register SI (16))
  (get (index) (raw-reg h-gr-x index))
  (set (index val) (set-quiet (raw-reg h-gr-x index) val))
)

; FIXME: get and set semantics?  Unknown how to split semantics best; with
; get/set semantics or within the insn specification.  Doing the former for
; now.  Should use different names for pre-v10.
; FIXME: No dccr for v0 and v3.  Different high flag bits.
(cris-d-hwregf-p h-sr SI 16)
(define-pmacro
  (cris-h-sr machver)
  (define-hardware
    (semantic-name h-sr-x)
    (name (.sym h-sr-v machver))
    (attrs (MACH (.sym crisv machver)))
    (comment (.str "Special registers for v" machver))
    (type register SI (16))
    (indices extern-keyword p-names-v10)
    (get
     (index)
     (cond
      SI
      ((orif (orif (eq index (regno p0)) (eq index (regno p4)))
	     (eq index (regno p8))) 0)
      ((eq index (regno vr)) machver)
      ((orif (eq index (regno ccr))
	     (eq index (regno dccr)))
       ; Return "P U I X N Z V C" for the low 8 bits.
       ; FIXME: More bits.
       (or SI
	   (and SI (raw-reg SI h-sr-x (regno ccr)) #xffffff00)
	   (or
	    (zext SI (reg BI h-cbit))
	    (or
	     (sll (zext SI (reg BI h-vbit)) 1)
	     (or
	      (sll (zext SI (reg BI h-zbit)) 2)
	      (or
	       (sll (zext SI (reg BI h-nbit)) 3)
	       (or
		(sll (zext SI (reg BI h-xbit)) 4)
		(or
		 (sll (zext SI (reg BI h-ibit)) 5)
		 (or
		  (sll (zext SI (reg BI h-ubit)) 6)
		  (or
		   (sll (zext SI (reg BI h-pbit)) 7)
		   0))))))))))
      (else (raw-reg SI h-sr-x index))))
    (set
     (index val)
     (cond
      ((orif (orif (eq index (regno p0)) (eq index (regno p4)))
	     (orif (eq index (regno p8)) (eq index (regno vr))))
       (nop))
      ((orif (eq index (regno ccr)) (eq index (regno dccr)))
       (sequence
	 ()
	 (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0))
	 (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0))
	 (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0))
	 (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0))
	 (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0))
	 (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0))
	 (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0))
	 (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0))
	 (set-quiet (raw-reg SI h-sr-x (regno ccr)) val)
	 (set-quiet (raw-reg SI h-sr-x (regno dccr)) val)))
      (else (set-quiet (raw-reg SI h-sr-x index) val)))))
)

(cris-h-sr 0)
(cris-h-sr 3)
(cris-h-sr 8)
(cris-h-sr 10)

(define-hardware
  (semantic-name h-sr-x)
  (name h-sr-v32)
  (attrs MACH-V32)
  (comment "Special registers for v32")
  (type register SI (16))
  (indices extern-keyword p-names-v32)

  (get
   (index)
   (cond
    SI
    ((orif (orif (eq index (regno p0)) (eq index (regno p4)))
	   (eq index (regno p8))) 0)
    ((eq index (regno vr)) 32)
    ((eq index (regno ccs))
     ; Return "S R P U I X N Z V C" for the low 10 bits.
     (or SI
	 (and SI (raw-reg SI h-sr-x (regno ccs)) #x3ffffc00)
	 (or
	  (zext SI (reg BI h-cbit))
	  (or
	   (sll (zext SI (reg BI h-vbit)) 1)
	   (or
	    (sll (zext SI (reg BI h-zbit)) 2)
	    (or
	     (sll (zext SI (reg BI h-nbit)) 3)
	     (or
	      (sll (zext SI (reg BI h-xbit)) 4)
	      (or
	       (sll (zext SI (reg BI h-ibit)) 5)
	       (or
		(sll (zext SI (reg BI h-ubit)) 6)
		(or
		 (sll (zext SI (reg BI h-pbit)) 7)
		 (or
		  (sll (zext SI (reg BI h-rbit)) 8)
		  (or
		   (sll (zext SI (reg BI h-sbit)) 9)
		   (or
		    (sll (zext SI (reg BI h-mbit)) 30)
		    (or
		     (sll (zext SI (reg BI h-qbit)) 31)
		     0))))))))))))))
    ((eq index (regno usp))
     ; In user mode, return general stack pointer.
     (if BI (reg BI h-ubit)
	 (raw-reg SI h-gr-x (regno sp))
	 (raw-reg SI h-sr-x (regno usp))))
    (else (raw-reg SI h-sr-x index))))

  (set
   (index val)
   (cond
    ((orif (orif (eq index (regno p0)) (eq index (regno p4)))