sh64-compact.cpu

(dshci ldsl-pr "Load status register (PR), post-increment"
       ()
       "lds.l @${rn}+, pr"
       (+ (f-op4 4) rn (f-sub8 38))
       (sequence ()
		 (set pr (mem SI rn))
		 (set rn (add rn 4))))

(dshci macl "Multiply and accumulate (long)"
       ()
       "mac.l @${rm}+, @${rn}+"
       (+ (f-op4 0) rn rm (f-sub4 15))
       (sequence ((DI tmpry) (DI mac) (DI result) (SI x) (SI y))
		 (set x (mem SI rn))
		 (set rn (add rn 4))
		 (if (eq (index-of rn) (index-of rm))
		     (sequence ()
			       (set rn (add rn 4))
			       (set rm (add rm 4))))
		 (set y (mem SI rm))
		 (set rm (add rm 4))
		 (set tmpry (mul (zext DI x) (zext DI y)))
		 (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
		 (set result (add mac tmpry))
		 (sequence ()
			   (if sbit
			       (sequence ((SI min) (SI max))
					 (set max (srl (inv DI 0) 16))
					; Preserve bit 48 for sign.
					 (set min (srl (inv DI 0) 15))
					 (if (gt result max)
					     (set result max)
					     (if (lt result min)
						 (set result min)))))
			   (set mach (subword SI result 0))
			   (set macl (subword SI result 1)))))

(dshci macw "Multiply and accumulate (word)"
       ()
       "mac.w @${rm}+, @${rn}+"
       (+ (f-op4 4) rn rm (f-sub4 15))
       (sequence ((SI tmpry) (DI mac) (DI result) (HI x) (HI y))
		 (set x (mem HI rn))
		 (set rn (add rn 2))
		 (if (eq (index-of rn) (index-of rm))
		     (sequence ()
			       (set rn (add rn 2))
			       (set rm (add rm 2))))
		 (set y (mem HI rm))
		 (set rm (add rm 2))
		 (set tmpry (mul (zext SI x) (zext SI y)))
		 (if sbit
		     (sequence ()
			       (if (add-oflag tmpry macl 0)
				   (set mach 1))
			       (set macl (add tmpry macl)))
		     (sequence ()
			       (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
			       (set result (add mac (ext DI tmpry)))
			       (set mach (subword SI result 0))
			       (set macl (subword SI result 1))))))

(dshci mov "Move"
       ()
       "mov $rm64, $rn64"
       (+ (f-op4 6) rn64 rm64 (f-sub4 3))
       (set rn64 rm64))

(dshci movi "Move immediate"
       ()
       "mov #$imm8, $rn"
       (+ (f-op4 14) rn imm8)
       (set rn (ext DI (and QI imm8 255))))

(dshci movb1 "Store byte to memory (register indirect w/ zero displacement)"
       ()
       "mov.b $rm, @$rn"
       (+ (f-op4 2) rn rm (f-sub4 0))
       (set (mem UQI rn) (subword UQI rm 3)))

(dshci movb2 "Store byte to memory (register indirect w/ pre-decrement)"
       ()
       "mov.b $rm, @-$rn"
       (+ (f-op4 2) rn rm (f-sub4 4))
       (sequence ((DI addr))
		 (set addr (sub rn 1))
		 (set (mem UQI addr) (subword UQI rm 3))
		 (set rn addr)))

(dshci movb3 "Store byte to memory (register/register indirect)"
       ()
       "mov.b $rm, @(r0,$rn)"
       (+ (f-op4 0) rn rm (f-sub4 4))
       (set (mem UQI (add r0 rn)) (subword UQI rm 3)))

(dshci movb4 "Store byte to memory (GBR-relative w/ displacement)"
       ()
       "mov.b r0, @($imm8, gbr)"
       (+ (f-op8 #xc0) imm8)
       (sequence ((DI addr))
		 (set addr (add gbr imm8))
		 (set (mem UQI addr) (subword UQI r0 3))))

(dshci movb5 "Store byte to memory (register indirect w/ displacement)"
       ()
       "mov.b r0, @($imm4, $rm)"
       (+ (f-op8 #x80) rm imm4)
       (sequence ((DI addr))
		 (set addr (add rm imm4))
		 (set (mem UQI addr) (subword UQI r0 3))))

(dshci movb6 "Load byte from memory (register indirect w/ zero displacement)"
       ()
       "mov.b @$rm, $rn"
       (+ (f-op4 6) rn rm (f-sub4 0))
       (set rn (ext SI (mem QI rm))))

(dshci movb7 "Load byte from memory (register indirect w/ post-increment)"
       ()
       "mov.b @${rm}+, $rn"
       (+ (f-op4 6) rn rm (f-sub4 4))
       (sequence ((QI data))
		 (set data (mem QI rm))
		 (if (eq (index-of rm) (index-of rn))
		     (set rm (ext SI data))
		     (set rm (add rm 1)))
		 (set rn (ext SI data))))

(dshci movb8 "Load byte from memory (register/register indirect)"
       ()
       "mov.b @(r0, $rm), $rn"
       (+ (f-op4 0) rn rm (f-sub4 12))
       (set rn (ext SI (mem QI (add r0 rm)))))

(dshci movb9 "Load byte from memory (GBR-relative with displacement)"
       ()
       "mov.b @($imm8, gbr), r0"
       (+ (f-op8 #xc4) imm8)
       (set r0 (ext SI (mem QI (add gbr imm8)))))

(dshci movb10 "Load byte from memory (register indirect w/ displacement)"
       ()
       "mov.b @($imm4, $rm), r0"
       (+ (f-op8 #x84) rm imm4)
       (set r0 (ext SI (mem QI (add rm imm4)))))

(dshci movl1 "Store long word to memory (register indirect w/ zero displacement)"
       ()
       "mov.l $rm, @$rn"
       (+ (f-op4 2) rn rm (f-sub4 2))
       (set (mem SI rn) rm))

(dshci movl2 "Store long word to memory (register indirect w/ pre-decrement)"
       ()
       "mov.l $rm, @-$rn"
       (+ (f-op4 2) rn rm (f-sub4 6))
       (sequence ((SI addr))
		 (set addr (sub rn 4))
		 (set (mem SI addr) rm)
		 (set rn addr)))

(dshci movl3 "Store long word to memory (register/register indirect)"
       ()
       "mov.l $rm, @(r0, $rn)"
       (+ (f-op4 0) rn rm (f-sub4 6))
       (set (mem SI (add r0 rn)) rm))

(dshci movl4 "Store long word to memory (GBR-relative w/ displacement)"
       ()
       "mov.l r0, @($imm8x4, gbr)"
       (+ (f-op8 #xc2) imm8x4)
       (set (mem SI (add gbr imm8x4)) r0))

(dshci movl5 "Store long word to memory (register indirect w/ displacement)"
       ()
       "mov.l $rm, @($imm4x4, $rn)"
       (+ (f-op4 1) rn rm imm4x4)
       (set (mem SI (add rn imm4x4)) rm))

(dshci movl6 "Load long word to memory (register indirect w/ zero displacement)"
       ()
       "mov.l @$rm, $rn"
       (+ (f-op4 6) rn rm (f-sub4 2))
       (set rn (mem SI rm)))

(dshci movl7 "Load long word from memory (register indirect w/ post-increment)"
       ()
       "mov.l @${rm}+, $rn"
       (+ (f-op4 6) rn rm (f-sub4 6))
       (sequence ()
		 (set rn (mem SI rm))
		 (if (eq (index-of rm) (index-of rn))
		     (set rm rn)
		     (set rm (add rm 4)))))

(dshci movl8 "Load long word from memory (register/register indirect)"
       ()
       "mov.l @(r0, $rm), $rn"
       (+ (f-op4 0) rn rm (f-sub4 14))
       (set rn (mem SI (add r0 rm))))

(dshci movl9 "Load long word from memory (GBR-relative w/ displacement)"
       ()
       "mov.l @($imm8x4, gbr), r0"
       (+ (f-op8 #xc6) imm8x4)
       (set r0 (mem SI (add gbr imm8x4))))

(dshci movl10 "Load long word from memory (PC-relative w/ displacement)"
       (ILLSLOT)
       "mov.l @($imm8x4, pc), $rn"
       (+ (f-op4 13) rn imm8x4)
       (set rn (mem SI (add imm8x4 (and (add pc 4) (inv 3))))))

(dshci movl11 "Load long word from memory (register indirect w/ displacement)"
       ()
       "mov.l @($imm4x4, $rm), $rn"
       (+ (f-op4 5) rn rm imm4x4)
       (set rn (mem SI (add rm imm4x4))))

(dshci movw1 "Store word to memory (register indirect w/ zero displacement)"
       ()
       "mov.w $rm, @$rn"
       (+ (f-op4 2) rn rm (f-sub4 1))
       (set (mem HI rn) (subword HI rm 1)))

(dshci movw2 "Store word to memory (register indirect w/ pre-decrement)"
       ()
       "mov.w $rm, @-$rn"
       (+ (f-op4 2) rn rm (f-sub4 5))
       (sequence ((DI addr))
		 (set addr (sub rn 2))
		 (set (mem HI addr) (subword HI rm 1))
		 (set rn addr)))

(dshci movw3 "Store word to memory (register/register indirect)"
       ()
       "mov.w $rm, @(r0, $rn)"
       (+ (f-op4 0) rn rm (f-sub4 5))
       (set (mem HI (add r0 rn)) (subword HI rm 1)))

(dshci movw4 "Store word to memory (GBR-relative w/ displacement)"
       ()
       "mov.w r0, @($imm8x2, gbr)"
       (+ (f-op8 #xc1) imm8x2)
       (set (mem HI (add gbr imm8x2)) (subword HI r0 1)))

(dshci movw5 "Store word to memory (register indirect w/ displacement)"
       ()
       "mov.w r0, @($imm4x2, $rn)"
       (+ (f-op8 #x81) rn imm4x2)
       (set (mem HI (add rn imm4x2)) (subword HI r0 1)))

(dshci movw6 "Load word from memory (register indirect w/ zero displacement)"
       ()
       "mov.w @$rm, $rn"
       (+ (f-op4 6) rn rm (f-sub4 1))
       (set rn (ext SI (mem HI rm))))

(dshci movw7 "Load word from memory (register indirect w/ post-increment)"
       ()
       "mov.w @${rm}+, $rn"
       (+ (f-op4 6) rn rm (f-sub4 5))
       (sequence ((HI data))
		 (set data (mem HI rm))
		 (if (eq (index-of rm) (index-of rn))
		     (set rm (ext SI data))
		     (set rm (add rm 2)))
		 (set rn (ext SI data))))

(dshci movw8 "Load word from memory (register/register indirect)"
       ()
       "mov.w @(r0, $rm), $rn"
       (+ (f-op4 0) rn rm (f-sub4 13))
       (set rn (ext SI (mem HI (add r0 rm)))))

(dshci movw9 "Load word from memory (GBR-relative w/ displacement)"
       ()
       "mov.w @($imm8x2, gbr), r0"
       (+ (f-op8 #xc5) imm8x2)
       (set r0 (ext SI (mem HI (add gbr imm8x2)))))

(dshci movw10 "Load word from memory (PC-relative w/ displacement)"
       (ILLSLOT)
       "mov.w @($imm8x2, pc), $rn"
       (+ (f-op4 9) rn imm8x2)
       (set rn (ext SI (mem HI (add (add pc 4) imm8x2)))))

(dshci movw11 "Load word from memory (register indirect w/ displacement)"
       ()
       "mov.w @($imm4x2, $rm), r0"
       (+ (f-op8 #x85) rm imm4x2)
       (set r0 (ext SI (mem HI (add rm imm4x2)))))

(dshci mova "Move effective address"
       (ILLSLOT)
       "mova @($imm8x4, pc), r0"
       (+ (f-op8 #xc7) imm8x4)
       (set r0 (add (and (add pc 4) (inv 3)) imm8x4)))

(dshci movcal "Move with cache block allocation"
       ()
       "movca.l r0, @$rn"
       (+ (f-op4 0) rn (f-sub8 #xc3))
       (set (mem SI rn) r0))
       
(dshci movt "Move t-bit"
       ()
       "movt $rn"
       (+ (f-op4 0) rn (f-sub8 41))
       (set rn (zext SI tbit)))

(dshci mull "Multiply"
       ()
       "mul.l $rm, $rn"
       (+ (f-op4 0) rn rm (f-sub4 7))
       (set macl (mul rm rn)))

(dshci mulsw "Multiply words (signed)"
       ()
       "muls.w $rm, $rn"
       (+ (f-op4 2) rn rm (f-sub4 15))
       (set macl (mul (ext SI (subword HI rm 1)) (ext SI (subword HI rn 1)))))

(dshci muluw "Multiply words (unsigned)"
       ()
       "mulu.w $rm, $rn"
       (+ (f-op4 2) rn rm (f-sub4 14))
       (set macl (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))))

(dshci neg "Negate"
       ()
       "neg $rm, $rn"
       (+ (f-op4 6) rn rm (f-sub4 11))
       (set rn (neg rm)))

(dshci negc "Negate with carry"
       ()
       "negc $rm, $rn"
       (+ (f-op4 6) rn rm (f-sub4 10))
       (sequence ((BI flag))
		 (set flag (sub-cflag 0 rm tbit))
		 (set rn (subc 0 rm tbit))
		 (set tbit flag)))

(dshci nop "No operation"
       ()
       "nop"
       (+ (f-op16 9))
       (nop))

(dshci not "Bitwise NOT"
       ()
       "not $rm64, $rn64"
       (+ (f-op4 6) rn64 rm64 (f-sub4 7))
       (set rn64 (inv rm64)))

(dshci ocbi "Invalidate operand cache block"
       ()
       "ocbi @$rn"
       (+ (f-op4 0) rn (f-sub8 147))
       (unimp "ocbi"))

(dshci ocbp "Purge operand cache block"
       ()
       "ocbp @$rn"
       (+ (f-op4 0) rn (f-sub8 163))
       (unimp "ocbp"))

(dshci ocbwb "Write back operand cache block"
       ()
       "ocbwb @$rn"
       (+ (f-op4 0) rn (f-sub8 179))
       (unimp "ocbwb"))

(dshci or "Bitwise OR"
       ()
       "or $rm64, $rn64"
       (+ (f-op4 2) rn64 rm64 (f-sub4 11))
       (set rn64 (or rm64 rn64)))

(dshci ori "Bitwise OR immediate"
       ()
       "or #$uimm8, r0"
       (+ (f-op8 #xcb) uimm8)
       (set r0 (or r0 (zext DI uimm8))))

(dshci orb "Bitwise OR immediate"
       ()
       "or.b #$imm8, @(r0, gbr)"
       (+ (f-op8 #xcf) imm8)
       (sequence ((DI addr) (UQI data))
		 (set addr (add r0 gbr))
		 (set data (or (mem UQI addr) imm8))
		 (set (mem UQI addr) data)))

(dshci pref "Prefetch data"
       ()
       "pref @$rn"
       (+ (f-op4 0) rn (f-sub8 131))
       (unimp "pref"))

(dshci rotcl "Rotate with carry left"
       ()
       "rotcl $rn"
       (+ (f-op4 4) rn (f-sub8 36))
       (sequence ((BI temp))
		 (set temp (srl rn 31))
		 (set rn (or (sll rn 1) tbit))
		 (set tbit (if BI temp 1 0))))

(dshci rotcr "Rotate with carry right"
       ()
       "rotcr $rn"
       (+ (f-op4 4) rn (f-sub8 37))
       (sequence ((BI lsbit) (SI temp))
		 (set lsbit (if BI (eq (and rn 1) 0) 0 1))
		 (set temp tbit)
		 (set rn (or (srl rn 1) (sll temp 31)))
		 (set tbit (if BI lsbit 1 0))))

(dshci rotl "Rotate left"
       ()
       "rotl $rn"
       (+ (f-op4 4) rn (f-sub8 4))
       (sequence ((BI temp))
		 (set temp (srl rn 31))
		 (set rn (or (sll rn 1) temp))
		 (set tbit (if BI temp 1 0))))

(dshci rotr "Rotate right"
       ()
       "rotr $rn"
       (+ (f-op4 4) rn (f-sub8 5))
       (sequence ((BI lsbit) (SI temp))
		 (set lsbit (if BI (eq (and rn 1) 0) 0 1))
		 (set temp lsbit)
		 (set rn (or (srl rn 1) (sll temp 31)))
		 (set tbit (if BI lsbit 1 0))))

(dshci rts "Return from subroutine"
       ()
       "rts"
       (+ (f-op16 11))
       (delay 1 (set pc pr)))

(dshci sets "Set S-bit"
       ()
       "sets"
       (+ (f-op16 88))
       (set sbit 1))

(dshci sett "Set T-bit"
       ()
       "sett"
       (+ (f-op16 24))
       (set tbit 1))

(dshci shad "Shift arithmetic dynamic"
       ()
       "shad $rm, $rn"
       (+ (f-op4 4) rn rm (f-sub4 12))
       (sequence ((QI shamt))
		 (set shamt (and QI rm 31))
		 (if (ge rm 0)
		     (set rn (sll rn shamt))
		     (if (ne shamt 0)
			 (set rn (sra rn (sub 32 shamt)))
			 (if (lt rn 0)
			     (set rn (neg 1))
			     (set rn 0))))))

(dshci shal "Shift left arithmetic one bit"
       ()
       "shal $rn"
       (+ (f-op4 4) rn (f-sub8 32))
       (sequence ((BI t))
		 (set t (srl rn 31))
		 (set rn (sll rn 1))
		 (set tbit (if BI t 1 0))))

(dshci shar "Shift right arithmetic one bit"
       ()
       "shar $rn"
       (+ (f-op4 4) rn (f-sub8 33))
       (sequence ((BI t))
		 (set t (and rn 1))
		 (set rn (sra rn 1))
		 (set tbit (if BI t 1 0))))

(dshci shld "Shift logical dynamic"
       ()
       "shld $rm, $rn"
       (+ (f-op4 4) rn rm (f-sub4 13))
       (sequence ((QI shamt))
		 (set shamt (and QI rm 31))
		 (if (ge rm 0)
		     (set rn (sll rn shamt))
		     (if (ne shamt 0)
			 (set rn (srl rn (sub 32 shamt)))
			 (set rn 0)))))

(dshci shll "Shift left logical one bit"
       ()
       "shll $rn"
       (+ (f-op4 4) rn (f-sub8 0))
       (sequence ((BI t))
		 (set t (srl rn 31))
		 (set rn (sll rn 1))
		 (set tbit (if BI t 1 0))))

(dshci shll2 "Shift left logical two bits"
       ()
       "shll2 $rn"
       (+ (f-op4 4) rn (f-sub8 8))
       (set rn (sll rn 2)))

(dshci shll8 "Shift left logical eight bits"
       ()
       "shll8 $rn"
       (+ (f-op4 4) rn (f-sub8 24))
       (set rn (sll rn 8)))

(dshci shll16 "Shift left logical sixteen bits"
       ()
       "shll16 $rn"
       (+ (f-op4 4) rn (f-sub8 40))
       (set rn (sll rn 16)))

(dshci shlr "Shift right logical one bit"
       ()
       "shlr $rn"
       (+ (f-op4 4) rn (f-sub8 1))
       (sequence ((BI t))
		 (set t (and rn 1))
		 (set rn (srl rn 1))
		 (set tbit (if BI t 1 0))))

(dshci shlr2 "Shift right logical two bits"
       ()
       "shlr2 $rn"
       (+ (f-op4 4) rn (f-sub8 9))
       (set rn (srl rn 2)))

(dshci shlr8 "Shift right logical eight bits"
       ()
       "shlr8 $rn"
       (+ (f-op4 4) rn (f-sub8 25))
       (set rn (srl rn 8)))

(dshci shlr16 "Shift right logical sixteen bits"
       ()
       "shlr16 $rn"
       (+ (f-op4 4) rn (f-sub8 41))
       (set rn (srl rn 16)))

(dshci stc-gbr "Store control register (GBR)"
       ()
       "stc gbr, $rn"
       (+ (f-op4 0) rn (f-sub8 18))
       (set rn gbr))

(dshci stcl-gbr "Store control register (GBR)"
       ()
       "stc.l gbr, @-$rn"
       (+ (f-op4 4) rn (f-sub8 19))
       (sequence ((DI addr))
		 (set addr (sub rn 4))
		 (set (mem SI addr) gbr)
		 (set rn addr)))

(dshci sts-fpscr "Store status register (FPSCR)"
       ()
       "sts fpscr, $rn"
       (+ (f-op4 0) rn (f-sub8 106))
       (set rn fpscr))

(dshci stsl-fpscr "Store status register (FPSCR)"
       ()
       "sts.l fpscr, @-$rn"
       (+ (f-op4 4) rn (f-sub8 98))
       (sequence ((DI addr))
		 (set addr (sub rn 4))
		 (set (mem SI addr) fpscr)
		 (set rn addr)))

(dshci sts-fpul "Store status register (FPUL)"
       ()
       "sts fpul, $rn"
       (+ (f-op4 0) rn (f-sub8 90))
       (set rn (subword SI fpul 0)))

(dshci stsl-fpul "Store status register (FPUL)"
       ()
       "sts.l fpul, @-$rn"
       (+ (f-op4 4) rn (f-sub8 82))
       (sequence ((DI addr))
		 (set addr (sub rn 4))
		 (set (mem SF addr) fpul)
		 (set rn addr)))

(dshci sts-mach "Store status register (MACH)"
       ()
       "sts mach, $rn"
       (+ (f-op4 0) rn (f-sub8 10))
       (set rn mach))

(dshci stsl-mach "Store status register (MACH)"
       ()
       "sts.l mach, @-$rn"
       (+ (f-op4 4) rn (f-sub8 2))
       (sequence ((DI addr))
		 (set addr (sub rn 4))
		 (set (mem SI addr) mach)
		 (set rn addr)))

(dshci sts-macl "Store status register (MACL)"
       ()
       "sts macl, $rn"
       (+ (f-op4 0) rn (f-sub8 26))
       (set rn macl))

(dshci stsl-macl "Store status register (MACL)"
       ()
       "sts.l macl, @-$rn"
       (+ (f-op4 4) rn (f-sub8 18))
       (sequence ((DI addr))
		 (set addr (sub rn 4))
		 (set (mem SI addr) macl)
		 (set rn addr)))

(dshci sts-pr "Store status register (PR)"
       ()
       "sts pr, $rn"
       (+ (f-op4 0) rn (f-sub8 42))
       (set rn pr))

(dshci stsl-pr "Store status register (PR)"
       ()
       "sts.l pr, @-$rn"
       (+ (f-op4 4) rn (f-sub8 34))
       (sequence ((DI addr))
		 (set addr (sub rn 4))
		 (set (mem SI addr) pr)
		 (set rn addr)))

(dshci sub "Subtract"
       ()
       "sub $rm, $rn"
       (+ (f-op4 3) rn rm (f-sub4 8))
       (set rn (sub rn rm)))

(dshci subc "Subtract and detect carry"
       ()
       "subc $rm, $rn"
       (+ (f-op4 3) rn rm (f-sub4 10))
       (sequence ((BI flag))
		 (set flag (sub-cflag rn rm tbit))
		 (set rn (subc rn rm tbit))
		 (set tbit flag)))

(dshci subv "Subtract and detect overflow"
       ()
       "subv $rm, $rn"
       (+ (f-op4 3) rn rm (f-sub4 11))
       (sequence ((BI t))
		 (set t (sub-oflag rn rm 0))
		 (set rn (sub rn rm))
		 (set tbit (if BI t 1 0))))

(dshci swapb "Swap bytes"
       ()
       "swap.b $rm, $rn"
       (+ (f-op4 6) rn rm (f-sub4 8))
       (sequence ((UHI top-half) (UQI byte1) (UQI byte0))
		 (set top-half (subword HI rm 0))
		 (set byte1 (subword QI rm 2))
		 (set byte0 (subword QI rm 3))
		 (set rn (or SI (sll SI top-half 16) (or SI (sll SI byte0 8) byte1)))))

(dshci swapw "Swap words"
       ()
       "swap.w $rm, $rn"
       (+ (f-op4 6) rn rm (f-sub4 9))
       (set rn (or (srl rm 16) (sll rm 16))))

(dshci tasb "Test and set byte"
       ()
       "tas.b @$rn"
       (+ (f-op4 4) rn (f-sub8 27))
       (sequence ((UQI byte))
		 (set byte (mem UQI rn))
		 (set tbit (if BI (eq byte 0) 1 0))
		 (set byte (or byte 128))
		 (set (mem UQI rn) byte)))

(dshci trapa "Trap"
       (ILLSLOT)
       "trapa #$uimm8"
       (+ (f-op8 #xc3) uimm8)
       (c-call "sh64_compact_trapa" uimm8 pc))

(dshci tst "Test and set t-bit"
       ()
       "tst $rm, $rn"
       (+ (f-op4 2) rn rm (f-sub4 8))
       (set tbit (if BI (eq (and rm rn) 0) 1 0)))

(dshci tsti "Test and set t-bit immediate" 
       ()
       "tst #$uimm8, r0"
       (+ (f-op8 #xc8) uimm8)
       (set tbit (if BI (eq (and r0 (zext SI uimm8)) 0) 1 0)))

(dshci tstb "Test and set t-bit immedate with memory byte"
       ()
       "tst.b #$imm8, @(r0, gbr)"
       (+ (f-op8 #xcc) imm8)
       (sequence ((DI addr))
		 (set addr (add r0 gbr))
		 (set tbit (if BI (eq (and (mem UQI addr) imm8) 0) 1 0))))

(dshci xor "Exclusive OR"
       ()
       "xor $rm64, $rn64"
       (+ (f-op4 2) rn64 rm64 (f-sub4 10))
       (set rn64 (xor rn64 rm64)))

(dshci xori "Exclusive OR immediate"
       ()
       "xor #$uimm8, r0"
       (+ (f-op8 #xca) uimm8)
       (set (reg h-gr 0) (xor (reg h-gr 0) (zext DI uimm8))))

(dshci xorb "Exclusive OR immediate with memory byte"
       ()
       "xor.b #$imm8, @(r0, gbr)"
       (+ (f-op8 #xce) imm8)
       (sequence ((DI addr) (UQI data))
		 (set addr (add r0 gbr))
		 (set data (xor (mem UQI addr) imm8))
		 (set (mem UQI addr) data)))

(dshci xtrct "Extract"
       ()
       "xtrct $rm, $rn"
       (+ (f-op4 2) rn rm (f-sub4 13))
       (set rn (or (sll rm 16) (srl rn 16))))