README for GNU development tools This directory contains various GNU compilers, assemblers, linkers, debuggers, etc., plus their support routines, definitions, and documentation. If you are receiving this as part of a GDB release, see the file gdb/README. If with a binutils release, see binutils/README; if with a libg++ release, see libg++/README, etc. That'll give you info about this package -- supported targets, how to use it, how to report bugs, etc. It is now possible to automatically configure and build a variety of tools with one command. To build all of the tools contained herein, run the ``configure'' script here, e.g.: ./configure make To install them (by default in /usr/local/bin, /usr/local/lib, etc), then do: make install (If the configure script can't determine your type of computer, give it the name as an argument, for instance ``./configure sun4''. You can use the script ``config.sub'' to test whether a name is recognized; if it is, config.sub translates it to a triplet specifying CPU, vendor, and OS.) If you have more than one compiler on your system, it is often best to explicitly set CC in the environment before running configure, and to also set CC when running make. For example (assuming sh/bash/ksh): CC=gcc ./configure make A similar example using csh: setenv CC gcc ./configure make Much of the code and documentation enclosed is copyright by the Free Software Foundation, Inc. See the file COPYING or COPYING.LIB in the various directories, for a description of the GNU General Public License terms under which you can copy the files. REPORTING BUGS: Again, see gdb/README, binutils/README, etc., for info on where and how to report problems.
Stafford Horne
authored
This patch adds support for OpenRISC 64-bit FPU operations on 32-bit cores by using register pairs. The functionality has been added to OpenRISC architecture specification version 1.3 as per architecture proposal 14[0]. For supporting assembly of both 64-bit and 32-bit precision instructions we have defined CGEN_VALIDATE_INSN_SUPPORTED. This allows cgen to use 64-bit bit architecture assembly parsing on 64-bit toolchains and 32-bit architecture assembly parsing on 32-bit toolchains. Without this the assembler has issues parsing register pairs. This patch also contains a few fixes to the symantics for existing OpenRISC single and double precision FPU operations. [0] https://openrisc.io/proposals/orfpx64a32 cpu/ChangeLog: yyyy-mm-dd Andrey Bacherov <avbacherov@opencores.org> Stafford Horne <shorne@gmail.com> * or1k.cpu (ORFPX64A32-MACHS): New pmacro. (ORFPX-MACHS): Removed pmacro. * or1k.opc (or1k_cgen_insn_supported): New function. (CGEN_VALIDATE_INSN_SUPPORTED): Define macro. (parse_regpair, print_regpair): New functions. * or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder and add comments. (h-fdr): Update comment to indicate or64. (reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs. (h-fd32r): New hardware for 64-bit fpu registers. (h-i64r): New hardware for 64-bit int registers. * or1korbis.cpu (f-resv-8-1): New field. * or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS. (rDDF, rADF, rBDF): Update operand comment to indicate or64. (f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields. (h-roff1): New hardware. (double-field-and-ops mnemonic): New pmacro to generate operations rDD32F, rAD32F, rBD32F, rDDI and rADI. (float-regreg-insn): Update single precision generator to MACH ORFPX32-MACHS. Add generator for or32 64-bit instructions. (float-setflag-insn): Update single precision generator to MACH ORFPX32-MACHS. Fix double instructions from single to double precision. Add generator for or32 64-bit instructions. (float-cust-insn cust-num): Update single precision generator to MACH ORFPX32-MACHS. Add generator for or32 64-bit instructions. (lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to ORFPX32-MACHS. (lf-rem-d): Fix operation from mod to rem. (lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction. (lf-itof-d): Fix operands from single to double. (lf-ftoi-d): Update operand mode from DI to WI.