From e3b96e32ca8e5a127ee4142a36480ae60cb2693e Mon Sep 17 00:00:00 2001 From: Joel Sherrill <joel.sherrill@oarcorp.com> Date: Mon, 15 Dec 2008 19:48:06 +0000 Subject: [PATCH] 2008-12-15 Joel Sherrill <joel.sherrill@oarcorp.com> * ppc-instructions, ppc-spr-table: Add ability to read tbrl and tbru special registers. --- sim/ppc/ChangeLog | 5 +++++ sim/ppc/ppc-instructions | 8 ++++++++ sim/ppc/ppc-spr-table | 2 ++ 3 files changed, 15 insertions(+) diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog index 17f50cfd309..6e0febfa047 100644 --- a/sim/ppc/ChangeLog +++ b/sim/ppc/ChangeLog @@ -1,3 +1,8 @@ +2008-12-15 Joel Sherrill <joel.sherrill@oarcorp.com> + + * ppc-instructions, ppc-spr-table: Add ability + to read tbrl and tbru special registers. + 2008-11-18 Joel Sherrill <joel.sherrill@oarcorp.com> * configure: Regenerated. diff --git a/sim/ppc/ppc-instructions b/sim/ppc/ppc-instructions index 5f3e13319f6..66c26fc949c 100644 --- a/sim/ppc/ppc-instructions +++ b/sim/ppc/ppc-instructions @@ -3402,6 +3402,14 @@ void::function::invalid_zero_divide_operation:cpu *processor, unsigned_word cia, case spr_dec: *rT = cpu_get_decrementer(processor); break; + case spr_tbrl: + if (is_64bit_implementation) *rT = TB; + else *rT = EXTRACTED64(TB, 32, 63); + break; + case spr_tbru: + if (is_64bit_implementation) *rT = EXTRACTED64(TB, 0, 31); + else *rT = EXTRACTED64(TB, 0, 31); + break; case spr_tbu: case spr_tbl: /* NOTE - these SPR's are not readable. Use mftb[ul] */ diff --git a/sim/ppc/ppc-spr-table b/sim/ppc/ppc-spr-table index 221ccbeacf0..e224df97f40 100644 --- a/sim/ppc/ppc-spr-table +++ b/sim/ppc/ppc-spr-table @@ -32,6 +32,8 @@ SDR1:25:0:0 SRR0:26:0:0 SRR1:27:0:0 VRSAVE:256:0:0 +TBRL:268:0:0 +TBRU:269:0:0 SPRG0:272:0:0 SPRG1:273:0:0 SPRG2:274:0:0 -- GitLab