diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 3e6a8d8c4d0defb368ad077f9aff8d36b7aadf7f..09311d15aa95c84d7fdf2d51ce1dff5db828dfe7 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-04  Alan Modra  <amodra@gmail.com>
+
+	* m32r.cpu (f-disp8): Avoid left shift of negative values.
+	(f-disp16, f-disp24): Likewise.
+
 2019-12-23  Alan Modra  <amodra@gmail.com>
 
 	* iq2000.cpu (f-offset): Avoid left shift of negative values.
diff --git a/cpu/m32r.cpu b/cpu/m32r.cpu
index 003c848687a29e8d6b01ed346df6a7f4d4309cb8..a2395259b5b543cb5b77c6865ffb42f6069f8f92 100644
--- a/cpu/m32r.cpu
+++ b/cpu/m32r.cpu
@@ -478,13 +478,13 @@
 (dnf f-hi16      "high 16 bits"        (SIGN-OPT) 16 16)
 (df f-disp8      "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
     ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
-    ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
+    ((value pc) (add WI (mul WI value (const 4)) (and WI pc (const -4)))))
 (df f-disp16     "disp16"              (PCREL-ADDR RELOC) 16 16 INT
     ((value pc) (sra WI (sub WI value pc) (const 2)))
-    ((value pc) (add WI (sll WI value (const 2)) pc)))
+    ((value pc) (add WI (mul WI value (const 4)) pc)))
 (df f-disp24     "disp24"              (PCREL-ADDR RELOC) 8 24 INT
     ((value pc) (sra WI (sub WI value pc) (const 2)))
-    ((value pc) (add WI (sll WI value (const 2)) pc)))
+    ((value pc) (add WI (mul WI value (const 4)) pc)))
 
 (dnf f-op23      "op2.3"               ()  9 3)
 (dnf f-op3       "op3"                 () 14 2)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d72dcec0426823d60ec5e0ade4b8cfa39d3df4b8..5dfb1fceb3295e7c2be7ca42960076ad872a5b52 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2020-01-04  Alan Modra  <amodra@gmail.com>
+
+	* m32r-ibld.c: Regenerate.
+
 2020-01-04  Alan Modra  <amodra@gmail.com>
 
 	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c
index 9ab98cf142dd040beb8493daac5212f1128b6c1e..8d5ce60db6d45db8244e03c7378a31eee992f351 100644
--- a/opcodes/m32r-ibld.c
+++ b/opcodes/m32r-ibld.c
@@ -723,7 +723,7 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
-        value = ((((value) << (2))) + (pc));
+        value = ((((value) * (4))) + (pc));
         fields->f_disp16 = value;
       }
       break;
@@ -731,7 +731,7 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
-        value = ((((value) << (2))) + (pc));
+        value = ((((value) * (4))) + (pc));
         fields->f_disp24 = value;
       }
       break;
@@ -739,7 +739,7 @@ m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
       {
         long value;
         length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
-        value = ((((value) << (2))) + (((pc) & (-4))));
+        value = ((((value) * (4))) + (((pc) & (-4))));
         fields->f_disp8 = value;
       }
       break;