From 44e4546fa278122fb1ad708cf8d4835a5af0a11c Mon Sep 17 00:00:00 2001
From: Alan Modra <amodra@gmail.com>
Date: Mon, 3 Feb 2020 11:26:30 +1030
Subject: [PATCH] ubsan: m32c: left shift of negative value
cpu/
* m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
opcodes/
* m32c-ibld.c: Regenerate.
---
cpu/ChangeLog | 4 ++++
cpu/m32c.cpu | 8 ++++----
opcodes/ChangeLog | 4 ++++
opcodes/m32c-ibld.c | 4 ++--
4 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 5611cd19e2f..f67c869a868 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,7 @@
+2020-02-03 Alan Modra <amodra@gmail.com>
+
+ * m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
+
2020-02-01 Alan Modra <amodra@gmail.com>
* frv.cpu (f-u12): Multiply rather than left shift signed values.
diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu
index 48b5acdfbd0..ab65fc13626 100644
--- a/cpu/m32c.cpu
+++ b/cpu/m32c.cpu
@@ -781,12 +781,12 @@
(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; insert
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; insert
((value pc) (ext INT
(trunc HI
- (or (and (srl value 8) #x00ff)
- (and (sll value 8) #xff00))))) ; extract
+ (or (and (srl value 8) #xff)
+ (sll (and value #xff) 8))))) ; extract
)
;-------------------------------------------------------------
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6349ff07f76..126025a312f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2020-02-03 Alan Modra <amodra@gmail.com>
+
+ * m32c-ibld.c: Regenerate.
+
2020-02-01 Alan Modra <amodra@gmail.com>
* frv-ibld.c: Regenerate.
diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c
index 7083a575e1a..36231f26dd9 100644
--- a/opcodes/m32c-ibld.c
+++ b/opcodes/m32c-ibld.c
@@ -1401,7 +1401,7 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
case M32C_OPERAND_IMM_64_HI :
{
long value = fields->f_dsp_64_s16;
- value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))))));
+ value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) & (255))) << (8)))))));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 64, 0, 16, 32, total_length, buffer);
}
break;
@@ -2561,7 +2561,7 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
{
long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 64, 0, 16, 32, total_length, pc, & value);
- value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))))));
+ value = EXTHISI (((HI) (INT) (((((((UINT) (value) >> (8))) & (255))) | (((((value) & (255))) << (8)))))));
fields->f_dsp_64_s16 = value;
}
break;
--
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