From 1f33efec7c6d1357d7e867176cfb88942fc513a8 Mon Sep 17 00:00:00 2001
From: Yao Qi <yao.qi@linaro.org>
Date: Fri, 26 Feb 2016 15:00:36 +0000
Subject: [PATCH] Record right reg num of thumb special data instructions
When GDB decodes these thumb special data instructions, such as 'mov sp, r7'
the Rd is got incorrectly. According to the arch reference manual, the Rd
is DN:Rdn, in which DN is bit 7 and Rdn is bits 0 to 2. This patch fixes it.
gdb:
2016-02-26 Yao Qi <yao.qi@linaro.org>
* arm-tdep.c (thumb_record_ld_st_reg_offset): Fix the register
number of Rd.
---
gdb/ChangeLog | 5 +++++
gdb/arm-tdep.c | 8 ++++----
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index fe3aa3627f2..36cbef6e8a8 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2016-02-26 Yao Qi <yao.qi@linaro.org>
+
+ * arm-tdep.c (thumb_record_ld_st_reg_offset): Fix the register
+ number of Rd.
+
2016-02-25 Doug Evans <dje@google.com>
* remote-m32r-sdi.c (recv_char_data): Initialize val to avoid
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 17f6fc6c373..bd0ee97b269 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -11512,10 +11512,10 @@ thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
}
else
{
- /* Format 8; special data processing insns. */
- reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2);
- record_buf[0] = ARM_PS_REGNUM;
- record_buf[1] = reg_src1;
+ /* Format 8; special data processing insns. */
+ record_buf[0] = ARM_PS_REGNUM;
+ record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3
+ | bits (thumb_insn_r->arm_insn, 0, 2));
thumb_insn_r->reg_rec_count = 2;
}
}
--
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