1. 18 Feb, 2021 1 commit
  2. 11 Feb, 2021 1 commit
  3. 10 Feb, 2021 1 commit
  4. 06 Feb, 2021 1 commit
  5. 03 Feb, 2021 2 commits
  6. 02 Feb, 2021 2 commits
  7. 21 Sep, 2020 1 commit
  8. 14 Jan, 2020 2 commits
  9. 07 Sep, 2019 1 commit
  10. 17 Aug, 2019 1 commit
  11. 08 Aug, 2019 1 commit
    • Xavier Leroy's avatar
      AArch64 port · 7cdd676d
      Xavier Leroy authored
      This commit adds a back-end for the AArch64 architecture, namely ARMv8
      in 64-bit mode.
  12. 26 Apr, 2019 1 commit
    • Xavier Leroy's avatar
      Move Z definitions out of Integers and into Zbits · 08fd5faf
      Xavier Leroy authored
      The module Integers.Make contained lots of definitions and theorems
      about Z integers that were independent of the word size.  These
      definitions and theorems are useful outside Integers.Make, but
      it felt unnatural to fetch them from modules Int or Int64.
      This commit moves the word-size-independent definitions and theorems
      to a new module, lib/Zbits.v, and fixes their uses in the code base.
  13. 28 Apr, 2017 1 commit
    • Xavier Leroy's avatar
      RISC-V port and assorted changes · f642817f
      Xavier Leroy authored
      This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes.
      The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/
      This port required the following additional changes:
      - Integers: More properties about shrx
      - SelectOp: now provides smart constructors for mulhs and mulhu
      - SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu.
      - Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert.  Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library.
      - test/: add SIMU make variable to run tests through a simulator
      - test/regression/alignas.c: make sure _Alignas and _Alignof are not #define'd by C headers
      commit da14495c01cf4f66a928c2feff5c53f09bde837f
      Author: Xavier Leroy <xavier.leroy@inria.fr>
      Date:   Thu Apr 13 17:36:10 2017 +0200
          RISC-V port, continued
          Now working on Asmgen.
      commit 36f36eb3a5abfbb8805960443d087b6a83e86005
      Author: Xavier Leroy <xavier.leroy@inria.fr>
      Date:   Wed Apr 12 17:26:39 2017 +0200
          RISC-V port, first steps
          This port is based on Prashanth Mundkur's experimental RV32 port and brings it up to date with CompCert, and adds 64-bit support (RV64).  Work in progress.