1. 14 Jan, 2021 1 commit
    • Xavier Leroy's avatar
      RISC-V: fix FP calling conventions · 88567ce6
      Xavier Leroy authored
      This is a follow-up to e81d015e.
      
      In the RISC-V ABI, FP arguments to functions are passed in integer registers
      (or pairs of integer registers) in two cases:
      1- the FP argument is a variadic argument
      2- the FP argument is a fixed argument but all 8 FP registers reserved for
         parameter passing have been used already.
      
      The previous implementation handled only case 1, with some problems.
      
      This commit implements both 1 and 2.  To this end, 8 extra FP
      caller-save registers are used to hold the values of the FP arguments
      that must be passed in integer registers.  Fixup code moves these FP
      registers to integer registers / register pairs.  Symmetrically, at
      function entry, the integer registers / register pairs are moved back
      to the FP registers.
      
      8 extra FP registers is enough because there are only 8 integer
      registers used for parameter passing, so at most 8 FP arguments may
      need to be moved to integer registers.
      88567ce6
  2. 03 Jan, 2020 1 commit
  3. 21 Dec, 2019 1 commit
  4. 17 Jun, 2019 1 commit
    • Xavier Leroy's avatar
      Extended asm: print register names according to their types · ed0cfe4b
      Xavier Leroy authored
      When printing an extended asm code fragment, placeholders %n
      are replaced by register names.
      
      Currently we ignore the fact that some assemblers use different
      register names depending on the width of the data that resides
      in the register.
      
      For example, x86_64 uses %rax for a 64-bit quantity and %eax for
      a 32-bit quantity, but CompCert always prints %rax in extended asm
      statements.  This is problematic if we want to use 32-bit integer
      instructions in extended asm, e.g.
      
                   int x, y;
                   asm("addl %1, %0", "=r"(x), "r"(y));
      produces
                   addl %rax, %rdx
      
      which is syntactically incorrect.
      
      Another example is ARM FP registers: D0 is a double-precision float,
      but S0 is a single-precision float.
      
      This commit partially solves this issue by taking into account the
      Cminor type of the asm parameter when printing the corresponding register.
      Continuing the previous example,
      
                   int x, y;
                   asm("addl %1, %0", "=r"(x), "r"(y));
      now produces
                   addl %eax, %edx
      
      This is not perfect yet: we use Cminor types, because this is all we
      have at hand, and not source C types, hence "char" and "short" parameters
      are still printed like "int" parameters, which is not good for x86.
      (I.e. we produce %eax where GCC might have produced %al or %ax.)
      We'll leave this issue open.
      ed0cfe4b
  5. 10 May, 2019 1 commit
    • Bernhard Schommer's avatar
      Added options -fcommon and -fno-common (#164) · 1eaf745c
      Bernhard Schommer authored
      The option -fcommon controls whether uninitialized global
      variables are placed in the COMMON section. If the option is given
      in the negated form, -fno-common, variables are not placed in the
      COMMON section. They are placed in the same sections as gcc does.
      
      If the variables are not placed in the COMMON section merging of
      tentative definitions is inhibited and multiple definitions lead
      to a linker error, as it does for gcc.
      1eaf745c
  6. 12 Sep, 2018 1 commit
    • Bernhard Schommer's avatar
      Generate a nop instruction after some ais annotations (#137) · 591073be
      Bernhard Schommer authored
      * Generate a nop instruction after ais annotations.
      
      In order to prevent the merging of ais annotations with following
      Labels a nop instruction is inserted, but only if the annotation
      is followed immediately by a label.
      
      The insertion of nop instructions is performed during the
      expansion of builtin and pseudo assembler instructions and is
      processor independent, by inserting a __builtin_nop built-in.
      
      * Add Pnop instruction to ARM, RISC-V, and x86
      
      ARM as well as RISC-V don't have nop instructions that can
      be easily encoded by for example add with zero instructions.
      For x86 we used to use `mov X0, X0` for nop but this may
      not be as efficient as the true nop instruction.
      
      * Implement __builtin_nop on all supported target architectures.
      
      This builtin is not yet made available on the C side for all architectures.
      
      Bug 24067
      591073be
  7. 08 Mar, 2018 2 commits
  8. 06 Mar, 2018 1 commit
    • Bernhard Schommer's avatar
      Reactivated and improved ais annotations. · 7ca7e64a
      Bernhard Schommer authored
      The ais annotations are now handled in a separate file shared
      between all architectures. Also two different variants of
      replacements are supported, %e which expands to ais expressions
      and %l which also expands to an ais expression but is guaranted to
      be usable as l-value in the ais annotation. Otherwise the new
      warning is Wrong_is_parameter is generated.
      
      Also an error message is generated if floating point variables are
      used in ais annotations since a3 does not support them at the
      moment.
      
      Additionally an error message is generated for plain volatile
      variables used, since they will enforce a volatile load and result
      in the value being passed to the annotation instead of the address
      as other global variables.
      7ca7e64a
  9. 10 Nov, 2017 1 commit
  10. 09 Nov, 2017 1 commit
  11. 08 Nov, 2017 2 commits
  12. 06 Nov, 2017 1 commit
  13. 19 Oct, 2017 1 commit
    • Bernhard Schommer's avatar
      New support for inserting ais-annotations. · 6a010b47
      Bernhard Schommer authored
      The ais annotations can be inserted via the new ais variants of
      the builtin annotation. They mainly differe in that they have an
      address format specifier '%addr' which will be replaced by the
      adress in the binary.
      
      The implementation simply prints a label for the builtin call
      alongside a the text of the annotation as comment and inserts the
      annotation together as acii string in a separate section
      'ais_annotations' and replaces the usages of the address format
      specifiers by the address of the label of the builtin call.
      6a010b47
  14. 19 Jul, 2017 1 commit
  15. 28 Apr, 2017 1 commit
    • Xavier Leroy's avatar
      RISC-V port and assorted changes · f642817f
      Xavier Leroy authored
      This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes.
      
      The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/
      
      This port required the following additional changes:
      
      - Integers: More properties about shrx
      
      - SelectOp: now provides smart constructors for mulhs and mulhu
      
      - SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu.
      
      - Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert.  Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library.
      
      - test/: add SIMU make variable to run tests through a simulator
      
      - test/regression/alignas.c: make sure _Alignas and _Alignof are not #define'd by C headers
      
      commit da14495c01cf4f66a928c2feff5c53f09bde837f
      Author: Xavier Leroy <xavier.leroy@inria.fr>
      Date:   Thu Apr 13 17:36:10 2017 +0200
      
          RISC-V port, continued
      
          Now working on Asmgen.
      
      commit 36f36eb3a5abfbb8805960443d087b6a83e86005
      Author: Xavier Leroy <xavier.leroy@inria.fr>
      Date:   Wed Apr 12 17:26:39 2017 +0200
      
          RISC-V port, first steps
      
          This port is based on Prashanth Mundkur's experimental RV32 port and brings it up to date with CompCert, and adds 64-bit support (RV64).  Work in progress.
      f642817f