1. 14 Jan, 2021 1 commit
    • Xavier Leroy's avatar
      RISC-V: fix FP calling conventions · 88567ce6
      Xavier Leroy authored
      This is a follow-up to e81d015e.
      In the RISC-V ABI, FP arguments to functions are passed in integer registers
      (or pairs of integer registers) in two cases:
      1- the FP argument is a variadic argument
      2- the FP argument is a fixed argument but all 8 FP registers reserved for
         parameter passing have been used already.
      The previous implementation handled only case 1, with some problems.
      This commit implements both 1 and 2.  To this end, 8 extra FP
      caller-save registers are used to hold the values of the FP arguments
      that must be passed in integer registers.  Fixup code moves these FP
      registers to integer registers / register pairs.  Symmetrically, at
      function entry, the integer registers / register pairs are moved back
      to the FP registers.
      8 extra FP registers is enough because there are only 8 integer
      registers used for parameter passing, so at most 8 FP arguments may
      need to be moved to integer registers.
  2. 29 Dec, 2020 1 commit
    • Xavier Leroy's avatar
      Replace `omega` tactic with `lia` · aba0e740
      Xavier Leroy authored
      Since Coq 8.12, `omega` is flagged as deprecated and scheduled for removal.
      Also replace CompCert's homemade tactics `omegaContradiction`, `xomega`,
      and `xomegaContradiction` with `lia` and `extlia`.
      Turn back on the deprecation warning for uses of `omega`.
      Make the proof of `Ctypes.sizeof_pos` more robust to variations in `lia`.
  3. 25 Dec, 2020 2 commits
  4. 02 Mar, 2020 1 commit
    • Xavier Leroy's avatar
      Update the RISC-V calling conventions, continued (#227) · c11b1961
      Xavier Leroy authored
      Double FP arguments passed on stack were incorrectly aligned:
      they must be 8-aligned but were 4-aligned only.
      This was due to the use of `Location.typealign`, which is the minimal
      hardware-supported alignment for a given type, namely 1 word for type Tfloat.
      To get the correct alignments, `Location.typesize` must be used instead.
  5. 26 Feb, 2020 1 commit
    • Xavier Leroy's avatar
      Update the RISC-V calling conventions (#221) · 5003b8d9
      Xavier Leroy authored
      We were implementing the ABI described in the RISC-V Instruction Set
      Manual, version 2.1.  However, this ABI was superseded by the RISC-V
      ELF psABI specification.
      This commit changes the calling conventions to better match the ELF psABI
      specification.  This should greatly improve interoperability with code
      compiled by other RISC-V compilers.
      One incompatibility remains: when all 8 FP argument registers have been used, further FP arguments should be passed in integer argument registers if available, while this PR passes them on stack.
  6. 24 Feb, 2020 1 commit
    • Xavier Leroy's avatar
      Platform-independent implementation of Conventions.size_arguments (#222) · 08efc2a0
      Xavier Leroy authored
      The "size_arguments" function and its properties can be systematically
      derived from the "loc_arguments" function and its properties.
      Before, the RISC-V port used this derivation, and all other ports
      used hand-written "size_arguments" functions and proofs.
      This commit moves the definition of "size_arguments" to the
      platform-independent file backend/Conventions.v, using the systematic
      derivation, and removes the platform-specific definitions.
      This reduces code and proof size, and makes it easier to change the
      calling conventions.
  7. 21 Feb, 2020 2 commits
    • Xavier Leroy's avatar
      Support re-normalization of values returned by function calls · 28f23580
      Xavier Leroy authored
      Some ABIs leave more flexibility concerning function return values
      than CompCert expects.
      For example, the x86 ABI says that a function result of type "char" is
      returned in register AL, leaving the top 24 bits of register EAX
      unspecified, while CompCert expects EAX to contain 32 valid bits,
      namely the zero- or sign-extension of the 8-bit result.
      This commits adds a general mechanism to insert "re-normalization"
      conversions on the results of function calls.  Currently, it only
      deals with results of small integer types, and inserts zero- or
      sign-extensions if so instructed by a platform-dependent function,
      The conversions in question are inserted early in the front-end, so
      that they can be optimized away in the back-end.
      The semantic preservation proof is still conducted against the
      CompCert model, where the return values of functions are already
      normalized.  What the proof shows is that the extra conversions have
      no effect in this case.  In future work we could relax the CompCert model,
      allowing functions to return values that are not normalized.
    • Xavier Leroy's avatar
      Refine the type of function results in AST.signature · be0b1872
      Xavier Leroy authored
      Before it was "option typ".  Now it is a proper inductive type
      that can also express small integer types (8/16-bit unsigned/signed integers).
      One benefit is that external functions get more precise types that
      control better their return values.  As a consequence,
      the CompCert C type preservation property now holds unconditionally,
      without extra typing hypotheses on external functions.
  8. 22 Sep, 2017 2 commits
    • Bernhard Schommer's avatar
      Remove coq warnings (#28) · 8d5c6bb8
      Bernhard Schommer authored
      Replace deprecated functions and theorems from the Coq standard library (version 8.6) by their non-deprecated counterparts.
    • Bernhard Schommer's avatar
      Remove coq warnings (#28) · a36b3b75
      Bernhard Schommer authored
      Replace deprecated functions and theorems from the Coq standard library (version 8.6) by their non-deprecated counterparts.
  9. 26 Aug, 2017 1 commit
  10. 05 May, 2017 1 commit
  11. 28 Apr, 2017 1 commit
    • Xavier Leroy's avatar
      RISC-V port and assorted changes · f642817f
      Xavier Leroy authored
      This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes.
      The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/
      This port required the following additional changes:
      - Integers: More properties about shrx
      - SelectOp: now provides smart constructors for mulhs and mulhu
      - SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu.
      - Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert.  Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library.
      - test/: add SIMU make variable to run tests through a simulator
      - test/regression/alignas.c: make sure _Alignas and _Alignof are not #define'd by C headers
      commit da14495c01cf4f66a928c2feff5c53f09bde837f
      Author: Xavier Leroy <xavier.leroy@inria.fr>
      Date:   Thu Apr 13 17:36:10 2017 +0200
          RISC-V port, continued
          Now working on Asmgen.
      commit 36f36eb3a5abfbb8805960443d087b6a83e86005
      Author: Xavier Leroy <xavier.leroy@inria.fr>
      Date:   Wed Apr 12 17:26:39 2017 +0200
          RISC-V port, first steps
          This port is based on Prashanth Mundkur's experimental RV32 port and brings it up to date with CompCert, and adds 64-bit support (RV64).  Work in progress.