• Xavier Leroy's avatar
    RISC-V port and assorted changes · f642817f
    Xavier Leroy authored
    This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes.
    The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/
    This port required the following additional changes:
    - Integers: More properties about shrx
    - SelectOp: now provides smart constructors for mulhs and mulhu
    - SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu.
    - Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert.  Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library.
    - test/: add SIMU make variable to run tests through a simulator
    - test/regression/ali...
Machine.ml 6.1 KB